Search

Sheila V. Clark

Examiner (ID: 7169, Phone: (571)272-1725 , Office: P/2896 )

Most Active Art Unit
2815
Art Unit(s)
2607, 2896, 2891, 2504, 2503, 2508, 2815, 2823
Total Applications
3274
Issued Applications
2860
Pending Applications
49
Abandoned Applications
366

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16233912 [patent_doc_number] => 10741475 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-11 [patent_title] => Delivery roll and method for manufacturing thereof [patent_app_type] => utility [patent_app_number] => 16/262979 [patent_app_country] => US [patent_app_date] => 2019-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 3963 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16262979 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/262979
Delivery roll and method for manufacturing thereof Jan 30, 2019 Issued
Array ( [id] => 16226297 [patent_doc_number] => 20200251414 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-06 [patent_title] => SEMICONDUCTOR DEVICE, PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 16/262924 [patent_app_country] => US [patent_app_date] => 2019-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6357 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16262924 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/262924
Semiconductor device, package structure and method of fabricating the same Jan 30, 2019 Issued
Array ( [id] => 16210393 [patent_doc_number] => 20200243383 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-30 [patent_title] => Interconnect with Self-Forming Wrap-All-Around Barrier Layer [patent_app_type] => utility [patent_app_number] => 16/262560 [patent_app_country] => US [patent_app_date] => 2019-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4987 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 21 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16262560 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/262560
Interconnect with self-forming wrap-all-around barrier layer Jan 29, 2019 Issued
Array ( [id] => 14587739 [patent_doc_number] => 20190221478 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-18 [patent_title] => DECOUPLED VIA FILL [patent_app_type] => utility [patent_app_number] => 16/249593 [patent_app_country] => US [patent_app_date] => 2019-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6421 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16249593 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/249593
Decoupled via fill Jan 15, 2019 Issued
Array ( [id] => 15547527 [patent_doc_number] => 10573553 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-25 [patent_title] => Semiconductor product and fabrication process [patent_app_type] => utility [patent_app_number] => 16/241143 [patent_app_country] => US [patent_app_date] => 2019-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 3490 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16241143 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/241143
Semiconductor product and fabrication process Jan 6, 2019 Issued
Array ( [id] => 14285283 [patent_doc_number] => 20190139926 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-09 [patent_title] => HIGH DENSITY SUBSTRATE ROUTING IN PACKAGE [patent_app_type] => utility [patent_app_number] => 16/239670 [patent_app_country] => US [patent_app_date] => 2019-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5022 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16239670 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/239670
High density substrate routing in package Jan 3, 2019 Issued
Array ( [id] => 16521611 [patent_doc_number] => 10872836 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-22 [patent_title] => Package structure for heat dissipation [patent_app_type] => utility [patent_app_number] => 16/230552 [patent_app_country] => US [patent_app_date] => 2018-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 50 [patent_figures_cnt] => 69 [patent_no_of_words] => 16745 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16230552 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/230552
Package structure for heat dissipation Dec 20, 2018 Issued
Array ( [id] => 14509481 [patent_doc_number] => 20190198395 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-27 [patent_title] => ELECTRICALLY CONDUCTIVE VIA(S) IN A SEMICONDUCTOR SUBSTRATE AND ASSOCIATED PRODUCTION METHOD [patent_app_type] => utility [patent_app_number] => 16/221930 [patent_app_country] => US [patent_app_date] => 2018-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7107 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16221930 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/221930
Electrically conductive via(s) in a semiconductor substrate and associated production method Dec 16, 2018 Issued
Array ( [id] => 14509383 [patent_doc_number] => 20190198346 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-27 [patent_title] => METHOD FOR CONTROLLING THE AMOUNT OF RADIATION HAVING A PREDETERMINED WAVELENGTH TO BE ABSORBED BY A STRUCTURE DISPOSED ON A SEMICONDUCTOR [patent_app_type] => utility [patent_app_number] => 16/220248 [patent_app_country] => US [patent_app_date] => 2018-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2808 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16220248 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/220248
Method for controlling the amount of radiation having a predetermined wavelength to be absorbed by a structure disposed on a semiconductor Dec 13, 2018 Issued
Array ( [id] => 16080639 [patent_doc_number] => 20200194306 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-18 [patent_title] => SELF-ALIGNED CUTS IN AN INTERCONNECT STRUCTURE [patent_app_type] => utility [patent_app_number] => 16/220565 [patent_app_country] => US [patent_app_date] => 2018-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4172 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16220565 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/220565
Self-aligned cuts in an interconnect structure Dec 13, 2018 Issued
Array ( [id] => 15791687 [patent_doc_number] => 10629575 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-04-21 [patent_title] => Stacked die semiconductor package with electrical interposer [patent_app_type] => utility [patent_app_number] => 16/219277 [patent_app_country] => US [patent_app_date] => 2018-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 8229 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16219277 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/219277
Stacked die semiconductor package with electrical interposer Dec 12, 2018 Issued
Array ( [id] => 16835234 [patent_doc_number] => 11011494 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-18 [patent_title] => Layer structures for making direct metal-to-metal bonds at low temperatures in microelectronics [patent_app_type] => utility [patent_app_number] => 16/218769 [patent_app_country] => US [patent_app_date] => 2018-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8479 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16218769 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/218769
Layer structures for making direct metal-to-metal bonds at low temperatures in microelectronics Dec 12, 2018 Issued
Array ( [id] => 16759821 [patent_doc_number] => 10978378 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-13 [patent_title] => Encapsulated leadless package having an at least partially exposed interior sidewall of a chip carrier [patent_app_type] => utility [patent_app_number] => 16/219415 [patent_app_country] => US [patent_app_date] => 2018-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 42 [patent_no_of_words] => 12676 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16219415 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/219415
Encapsulated leadless package having an at least partially exposed interior sidewall of a chip carrier Dec 12, 2018 Issued
Array ( [id] => 16835243 [patent_doc_number] => 11011503 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-18 [patent_title] => Direct-bonded optoelectronic interconnect for high-density integrated photonics [patent_app_type] => utility [patent_app_number] => 16/219693 [patent_app_country] => US [patent_app_date] => 2018-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6694 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16219693 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/219693
Direct-bonded optoelectronic interconnect for high-density integrated photonics Dec 12, 2018 Issued
Array ( [id] => 16148191 [patent_doc_number] => 10707172 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-07 [patent_title] => Component-embedded substrate, method of manufacturing the same, and high-frequency module [patent_app_type] => utility [patent_app_number] => 16/212750 [patent_app_country] => US [patent_app_date] => 2018-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 5691 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16212750 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/212750
Component-embedded substrate, method of manufacturing the same, and high-frequency module Dec 6, 2018 Issued
Array ( [id] => 16653424 [patent_doc_number] => 10930617 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-23 [patent_title] => Packaging method and package structure of wafer-level system-in-package [patent_app_type] => utility [patent_app_number] => 16/208307 [patent_app_country] => US [patent_app_date] => 2018-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 10862 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16208307 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/208307
Packaging method and package structure of wafer-level system-in-package Dec 2, 2018 Issued
Array ( [id] => 16536551 [patent_doc_number] => 10879164 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-29 [patent_title] => Integrated circuit electrostatic discharge bus structure and related method [patent_app_type] => utility [patent_app_number] => 16/207183 [patent_app_country] => US [patent_app_date] => 2018-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2466 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16207183 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/207183
Integrated circuit electrostatic discharge bus structure and related method Dec 1, 2018 Issued
Array ( [id] => 14110211 [patent_doc_number] => 20190096781 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-28 [patent_title] => 3DIC Packaging with Hot Spot Thermal Management Features [patent_app_type] => utility [patent_app_number] => 16/206903 [patent_app_country] => US [patent_app_date] => 2018-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5231 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16206903 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/206903
3DIC packaging with hot spot thermal management features Nov 29, 2018 Issued
Array ( [id] => 14317123 [patent_doc_number] => 20190148265 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-16 [patent_title] => SEMICONDUCTOR MODULE [patent_app_type] => utility [patent_app_number] => 16/202093 [patent_app_country] => US [patent_app_date] => 2018-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9964 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16202093 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/202093
Semiconductor module Nov 27, 2018 Issued
Array ( [id] => 14110285 [patent_doc_number] => 20190096818 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-28 [patent_title] => MANUFACTURING METHOD OF WIRING STRUCTURE AND WIRING STRUCTURE [patent_app_type] => utility [patent_app_number] => 16/189174 [patent_app_country] => US [patent_app_date] => 2018-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6403 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16189174 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/189174
Manufacturing method of wiring structure and wiring structure Nov 12, 2018 Issued
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