Sheila V. Clark

Array ( [id] => 4575605 [patent_doc_number] => 07859123 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-28 [patent_title] => 'Wire bonding structure and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 12/358604 [patent_app_country] => US [patent_app_date] => 2009-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 2641 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/859/07859123.pdf [firstpage_image] =>[orig_patent_app_number] => 12358604 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6224891 [patent_doc_number] => 20100181663 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-22 [patent_title] => 'LOW COMPRESSIVE FORCE, NON-SILICONE, HIGH THERMAL CONDUCTING FORMULATION FOR THERMAL INTERFACE MATERIAL AND PACKAGE' [patent_app_type] => utility [patent_app_number] => 12/357744 [patent_app_country] => US [patent_app_date] => 2009-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3127 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0181/20100181663.pdf [firstpage_image] =>[orig_patent_app_number] => 12357744 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 24969 [patent_doc_number] => 07795719 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-14 [patent_title] => 'Electro component package' [patent_app_type] => utility [patent_app_number] => 12/357643 [patent_app_country] => US [patent_app_date] => 2009-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1815 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/795/07795719.pdf [firstpage_image] =>[orig_patent_app_number] => 12357643 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4564333 [patent_doc_number] => 07846773 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-07 [patent_title] => 'Multi-chip semiconductor package' [patent_app_type] => utility [patent_app_number] => 12/356354 [patent_app_country] => US [patent_app_date] => 2009-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 4137 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/846/07846773.pdf [firstpage_image] =>[orig_patent_app_number] => 12356354 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4558479 [patent_doc_number] => 07821118 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-10-26 [patent_title] => 'Power distribution pattern for a ball grid array' [patent_app_type] => utility [patent_app_number] => 12/352743 [patent_app_country] => US [patent_app_date] => 2009-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4835 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/821/07821118.pdf [firstpage_image] =>[orig_patent_app_number] => 12352743 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5578728 [patent_doc_number] => 20090174074 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-09 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/351084 [patent_app_country] => US [patent_app_date] => 2009-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3565 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0174/20090174074.pdf [firstpage_image] =>[orig_patent_app_number] => 12351084 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5580767 [patent_doc_number] => 20090176113 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-09 [patent_title] => 'DISPLAY DEVICE AND SPUTTERING TARGET FOR PRODUCING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/349562 [patent_app_country] => US [patent_app_date] => 2009-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 14473 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0176/20090176113.pdf [firstpage_image] =>[orig_patent_app_number] => 12349562 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5377437 [patent_doc_number] => 20090189276 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-30 [patent_title] => 'SEMICONDUCTOR CHIP AND SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/348543 [patent_app_country] => US [patent_app_date] => 2009-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4658 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0189/20090189276.pdf [firstpage_image] =>[orig_patent_app_number] => 12348543 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 52969 [patent_doc_number] => 07772083 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-10 [patent_title] => 'Trench forming method and structure' [patent_app_type] => utility [patent_app_number] => 12/344733 [patent_app_country] => US [patent_app_date] => 2008-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2681 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/772/07772083.pdf [firstpage_image] =>[orig_patent_app_number] => 12344733 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4489149 [patent_doc_number] => 07884470 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-08 [patent_title] => 'Semiconductor packages with stiffening support for power delivery' [patent_app_type] => utility [patent_app_number] => 12/317434 [patent_app_country] => US [patent_app_date] => 2008-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 3006 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/884/07884470.pdf [firstpage_image] =>[orig_patent_app_number] => 12317434 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5432253 [patent_doc_number] => 20090166839 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-02 [patent_title] => 'SEMICONDUCTOR STACK DEVICE AND MOUNTING METHOD' [patent_app_type] => utility [patent_app_number] => 12/342603 [patent_app_country] => US [patent_app_date] => 2008-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4506 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0166/20090166839.pdf [firstpage_image] =>[orig_patent_app_number] => 12342603 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5432309 [patent_doc_number] => 20090166895 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-02 [patent_title] => 'CIRCUIT SUBSTRATE, CIRCUIT DEVICE AND MANUFACTURING PROCESS THEREOF' [patent_app_type] => utility [patent_app_number] => 12/342363 [patent_app_country] => US [patent_app_date] => 2008-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7286 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0166/20090166895.pdf [firstpage_image] =>[orig_patent_app_number] => 12342363 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5578720 [patent_doc_number] => 20090174066 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-09 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/341714 [patent_app_country] => US [patent_app_date] => 2008-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4610 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0174/20090174066.pdf [firstpage_image] =>[orig_patent_app_number] => 12341714 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5461758 [patent_doc_number] => 20090321958 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-31 [patent_title] => 'SEMICONDUCTOR DEVICE HAVING A SIMPLIFIED STACK AND METHOD FOR MANUFACTURING THEREOF' [patent_app_type] => utility [patent_app_number] => 12/341863 [patent_app_country] => US [patent_app_date] => 2008-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3986 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0321/20090321958.pdf [firstpage_image] =>[orig_patent_app_number] => 12341863 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4446052 [patent_doc_number] => 07863747 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-04 [patent_title] => 'Semiconductor chip, method of fabricating the same and semiconductor chip stack package' [patent_app_type] => utility [patent_app_number] => 12/340273 [patent_app_country] => US [patent_app_date] => 2008-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 3517 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/863/07863747.pdf [firstpage_image] =>[orig_patent_app_number] => 12340273 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6400914 [patent_doc_number] => 20100148337 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-17 [patent_title] => 'STACKABLE SEMICONDUCTOR PACKAGE AND PROCESS TO MANUFACTURE SAME' [patent_app_type] => utility [patent_app_number] => 12/336633 [patent_app_country] => US [patent_app_date] => 2008-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2465 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20100148337.pdf [firstpage_image] =>[orig_patent_app_number] => 12336633 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5192 [patent_doc_number] => 07816784 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-19 [patent_title] => 'Power quad flat no-lead semiconductor die packages with isolated heat sink for high-voltage, high-power applications, systems using the same, and methods of making the same' [patent_app_type] => utility [patent_app_number] => 12/337513 [patent_app_country] => US [patent_app_date] => 2008-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 5077 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/816/07816784.pdf [firstpage_image] =>[orig_patent_app_number] => 12337513 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6401082 [patent_doc_number] => 20100148363 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-17 [patent_title] => 'STEP CAVITY FOR ENHANCED DROP TEST PERFORMANCE IN BALL GRID ARRAY PACKAGE' [patent_app_type] => utility [patent_app_number] => 12/336273 [patent_app_country] => US [patent_app_date] => 2008-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2710 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20100148363.pdf [firstpage_image] =>[orig_patent_app_number] => 12336273 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5340654 [patent_doc_number] => 20090179304 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-16 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/336043 [patent_app_country] => US [patent_app_date] => 2008-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6248 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0179/20090179304.pdf [firstpage_image] =>[orig_patent_app_number] => 12336043 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6401113 [patent_doc_number] => 20100148371 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-17 [patent_title] => 'Via First Plus Via Last Technique for IC Interconnects' [patent_app_type] => utility [patent_app_number] => 12/334433 [patent_app_country] => US [patent_app_date] => 2008-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3049 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20100148371.pdf [firstpage_image] =>[orig_patent_app_number] => 12334433 [rel_patent_id] =>[rel_patent_doc_number] =>)