
Sheila V. Clark
Examiner (ID: 7169, Phone: (571)272-1725 , Office: P/2896 )
| Most Active Art Unit | 2815 |
| Art Unit(s) | 2607, 2896, 2891, 2504, 2503, 2508, 2815, 2823 |
| Total Applications | 3274 |
| Issued Applications | 2860 |
| Pending Applications | 49 |
| Abandoned Applications | 366 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 14999961
[patent_doc_number] => 20190318938
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-10-17
[patent_title] => SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 15/951093
[patent_app_country] => US
[patent_app_date] => 2018-04-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5823
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15951093
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/951093 | Semiconductor device package and method of manufacturing the same | Apr 10, 2018 | Issued |
Array
(
[id] => 14366951
[patent_doc_number] => 10304788
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2019-05-28
[patent_title] => Semiconductor power module to protect against short circuit event
[patent_app_type] => utility
[patent_app_number] => 15/950749
[patent_app_country] => US
[patent_app_date] => 2018-04-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 8847
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15950749
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/950749 | Semiconductor power module to protect against short circuit event | Apr 10, 2018 | Issued |
Array
(
[id] => 13349571
[patent_doc_number] => 20180226325
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-08-09
[patent_title] => Integrated Circuit (IC) Package with a Solder Receiving Area and Associated Methods
[patent_app_type] => utility
[patent_app_number] => 15/949541
[patent_app_country] => US
[patent_app_date] => 2018-04-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3168
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -29
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15949541
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/949541 | Integrated circuit (IC) package with a solder receiving area and associated methods | Apr 9, 2018 | Issued |
Array
(
[id] => 14036211
[patent_doc_number] => 10229861
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-03-12
[patent_title] => Power semiconductor device and package
[patent_app_type] => utility
[patent_app_number] => 15/947756
[patent_app_country] => US
[patent_app_date] => 2018-04-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 6
[patent_no_of_words] => 3158
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15947756
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/947756 | Power semiconductor device and package | Apr 5, 2018 | Issued |
Array
(
[id] => 14094021
[patent_doc_number] => 10242923
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-03-26
[patent_title] => Formulations containing mixed resin systems and the use thereof for wafer-level underfill for 3D TSV packages
[patent_app_type] => utility
[patent_app_number] => 15/945772
[patent_app_country] => US
[patent_app_date] => 2018-04-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 5874
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 139
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15945772
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/945772 | Formulations containing mixed resin systems and the use thereof for wafer-level underfill for 3D TSV packages | Apr 4, 2018 | Issued |
Array
(
[id] => 15139295
[patent_doc_number] => 10483133
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-11-19
[patent_title] => Method for fabricating a semiconductor chip panel
[patent_app_type] => utility
[patent_app_number] => 15/944306
[patent_app_country] => US
[patent_app_date] => 2018-04-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 21
[patent_no_of_words] => 4842
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15944306
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/944306 | Method for fabricating a semiconductor chip panel | Apr 2, 2018 | Issued |
Array
(
[id] => 15791681
[patent_doc_number] => 10629572
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-04-21
[patent_title] => Electronic package and method for fabricating the same
[patent_app_type] => utility
[patent_app_number] => 15/938271
[patent_app_country] => US
[patent_app_date] => 2018-03-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 7
[patent_no_of_words] => 3095
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15938271
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/938271 | Electronic package and method for fabricating the same | Mar 27, 2018 | Issued |
Array
(
[id] => 13950635
[patent_doc_number] => 10211096
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2019-02-19
[patent_title] => Semiconductor product and fabrication process
[patent_app_type] => utility
[patent_app_number] => 15/928492
[patent_app_country] => US
[patent_app_date] => 2018-03-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 14
[patent_no_of_words] => 3456
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 152
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15928492
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/928492 | Semiconductor product and fabrication process | Mar 21, 2018 | Issued |
Array
(
[id] => 16495752
[patent_doc_number] => 10861803
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2020-12-08
[patent_title] => Low cost millimeter wave integrated LTCC package and method of manufacturing
[patent_app_type] => utility
[patent_app_number] => 15/924787
[patent_app_country] => US
[patent_app_date] => 2018-03-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 21
[patent_no_of_words] => 7687
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 172
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15924787
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/924787 | Low cost millimeter wave integrated LTCC package and method of manufacturing | Mar 18, 2018 | Issued |
Array
(
[id] => 13320793
[patent_doc_number] => 20180211934
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-07-26
[patent_title] => RESIN SUBSTRATE, COMPONENT-MOUNTED RESIN SUBSTRATE, METHOD OF MANUFACTURING RESIN SUBSTRATE, AND METHOD OF MANUFACTURING COMPONENT-MOUNTED RESIN SUBSTRATE
[patent_app_type] => utility
[patent_app_number] => 15/924305
[patent_app_country] => US
[patent_app_date] => 2018-03-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5857
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 158
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15924305
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/924305 | Resin substrate, component-mounted resin substrate, method of manufacturing resin substrate, and method of manufacturing component-mounted resin substrate | Mar 18, 2018 | Issued |
Array
(
[id] => 16324144
[patent_doc_number] => 10784116
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-09-22
[patent_title] => Method of manufacturing semiconductor device, substrate processing apparatus, and recording medium
[patent_app_type] => utility
[patent_app_number] => 15/922500
[patent_app_country] => US
[patent_app_date] => 2018-03-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 14
[patent_no_of_words] => 18975
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15922500
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/922500 | Method of manufacturing semiconductor device, substrate processing apparatus, and recording medium | Mar 14, 2018 | Issued |
Array
(
[id] => 15234545
[patent_doc_number] => 10505003
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-12-10
[patent_title] => Semiconductor structure and manufacturing method thereof
[patent_app_type] => utility
[patent_app_number] => 15/921947
[patent_app_country] => US
[patent_app_date] => 2018-03-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 4851
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15921947
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/921947 | Semiconductor structure and manufacturing method thereof | Mar 14, 2018 | Issued |
Array
(
[id] => 12918013
[patent_doc_number] => 20180197847
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-07-12
[patent_title] => Package-on-Package Structures and Methods for Forming the Same
[patent_app_type] => utility
[patent_app_number] => 15/912807
[patent_app_country] => US
[patent_app_date] => 2018-03-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2716
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 61
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15912807
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/912807 | Package-on-package structures and methods for forming the same | Mar 5, 2018 | Issued |
Array
(
[id] => 14267615
[patent_doc_number] => 10283378
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-05-07
[patent_title] => Fluxing underfill compositions
[patent_app_type] => utility
[patent_app_number] => 15/899878
[patent_app_country] => US
[patent_app_date] => 2018-02-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 5927
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15899878
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/899878 | Fluxing underfill compositions | Feb 19, 2018 | Issued |
Array
(
[id] => 12849160
[patent_doc_number] => 20180174893
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-06-21
[patent_title] => VIA BLOCKING LAYER
[patent_app_type] => utility
[patent_app_number] => 15/898618
[patent_app_country] => US
[patent_app_date] => 2018-02-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8241
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15898618
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/898618 | Via blocking layer | Feb 17, 2018 | Issued |
Array
(
[id] => 12849034
[patent_doc_number] => 20180174851
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-06-21
[patent_title] => THIN FILM METAL SILICIDES AND METHODS FOR FORMATION
[patent_app_type] => utility
[patent_app_number] => 15/890465
[patent_app_country] => US
[patent_app_date] => 2018-02-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8024
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 6
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15890465
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/890465 | Thin film metal silicides and methods for formation | Feb 6, 2018 | Issued |
Array
(
[id] => 15427677
[patent_doc_number] => 10546777
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-01-28
[patent_title] => Conductive interconnect structures incorporating negative thermal expansion materials and associated systems, devices, and methods
[patent_app_type] => utility
[patent_app_number] => 15/889120
[patent_app_country] => US
[patent_app_date] => 2018-02-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 17
[patent_no_of_words] => 3805
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 65
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15889120
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/889120 | Conductive interconnect structures incorporating negative thermal expansion materials and associated systems, devices, and methods | Feb 4, 2018 | Issued |
Array
(
[id] => 12759607
[patent_doc_number] => 20180145037
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-05-24
[patent_title] => SEMICONDUCTOR PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 15/873784
[patent_app_country] => US
[patent_app_date] => 2018-01-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5333
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -22
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15873784
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/873784 | Semiconductor package structure and fabrication method thereof | Jan 16, 2018 | Issued |
Array
(
[id] => 12759637
[patent_doc_number] => 20180145047
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-05-24
[patent_title] => HIGH DENSITY SUBSTRATE ROUTING IN PACKAGE
[patent_app_type] => utility
[patent_app_number] => 15/873567
[patent_app_country] => US
[patent_app_date] => 2018-01-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4994
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15873567
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/873567 | High density substrate routing in package | Jan 16, 2018 | Issued |
Array
(
[id] => 12716836
[patent_doc_number] => 20180130778
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-05-10
[patent_title] => HIGH-FREQUENCY MODULE
[patent_app_type] => utility
[patent_app_number] => 15/866732
[patent_app_country] => US
[patent_app_date] => 2018-01-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3362
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -2
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15866732
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/866732 | High-frequency module | Jan 9, 2018 | Issued |