Search

Sheila V. Clark

Examiner (ID: 256, Phone: (571)272-1725 , Office: P/2896 )

Most Active Art Unit
2815
Art Unit(s)
2503, 2823, 2815, 2607, 2504, 2891, 2508, 2896
Total Applications
3274
Issued Applications
2860
Pending Applications
49
Abandoned Applications
366

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12738919 [patent_doc_number] => 20180138140 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-17 [patent_title] => METHOD OF FABRICATING SUBSTRATE STRUCTURE [patent_app_type] => utility [patent_app_number] => 15/867008 [patent_app_country] => US [patent_app_date] => 2018-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2062 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15867008 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/867008
Method of fabricating substrate structure Jan 9, 2018 Issued
Array ( [id] => 14333009 [patent_doc_number] => 10297533 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-21 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 15/854814 [patent_app_country] => US [patent_app_date] => 2017-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6405 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15854814 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/854814
Semiconductor device Dec 26, 2017 Issued
Array ( [id] => 13270901 [patent_doc_number] => 10147537 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-04 [patent_title] => Fluxgate device with low fluxgate noise [patent_app_type] => utility [patent_app_number] => 15/832884 [patent_app_country] => US [patent_app_date] => 2017-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 10723 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15832884 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/832884
Fluxgate device with low fluxgate noise Dec 5, 2017 Issued
Array ( [id] => 13071127 [patent_doc_number] => 10056349 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-21 [patent_title] => Manufacturing method of semiconductor device and semiconductor device thereof [patent_app_type] => utility [patent_app_number] => 15/831771 [patent_app_country] => US [patent_app_date] => 2017-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 75 [patent_no_of_words] => 15352 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15831771 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/831771
Manufacturing method of semiconductor device and semiconductor device thereof Dec 4, 2017 Issued
Array ( [id] => 13214699 [patent_doc_number] => 10121725 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-06 [patent_title] => Systems for thermal management and methods for the use thereof [patent_app_type] => utility [patent_app_number] => 15/811185 [patent_app_country] => US [patent_app_date] => 2017-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4036 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15811185 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/811185
Systems for thermal management and methods for the use thereof Nov 12, 2017 Issued
Array ( [id] => 13201515 [patent_doc_number] => 10115678 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-30 [patent_title] => Wire bond wires for interference shielding [patent_app_type] => utility [patent_app_number] => 15/804122 [patent_app_country] => US [patent_app_date] => 2017-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 23 [patent_no_of_words] => 8511 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15804122 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/804122
Wire bond wires for interference shielding Nov 5, 2017 Issued
Array ( [id] => 13060633 [patent_doc_number] => 10051735 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-14 [patent_title] => Packaging for high power integrated circuits and infrared emitter arrays [patent_app_type] => utility [patent_app_number] => 15/797233 [patent_app_country] => US [patent_app_date] => 2017-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 6588 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15797233 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/797233
Packaging for high power integrated circuits and infrared emitter arrays Oct 29, 2017 Issued
Array ( [id] => 12188939 [patent_doc_number] => 20180047875 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-15 [patent_title] => 'PROTECTIVE CAPPING LAYER FOR SPALLED GALLIUM NITRIDE' [patent_app_type] => utility [patent_app_number] => 15/791739 [patent_app_country] => US [patent_app_date] => 2017-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9137 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15791739 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/791739
Protective capping layer for spalled gallium nitride Oct 23, 2017 Issued
Array ( [id] => 14367387 [patent_doc_number] => 10305008 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-28 [patent_title] => Semiconductor module and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 15/787408 [patent_app_country] => US [patent_app_date] => 2017-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 8780 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15787408 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/787408
Semiconductor module and method for manufacturing the same Oct 17, 2017 Issued
Array ( [id] => 14603579 [patent_doc_number] => 10354986 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-16 [patent_title] => Hollow metal pillar packaging scheme [patent_app_type] => utility [patent_app_number] => 15/783619 [patent_app_country] => US [patent_app_date] => 2017-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 2942 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15783619 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/783619
Hollow metal pillar packaging scheme Oct 12, 2017 Issued
Array ( [id] => 13145811 [patent_doc_number] => 10090245 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-02 [patent_title] => Semiconductor device structure [patent_app_type] => utility [patent_app_number] => 15/728762 [patent_app_country] => US [patent_app_date] => 2017-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6473 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15728762 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/728762
Semiconductor device structure Oct 9, 2017 Issued
Array ( [id] => 13145795 [patent_doc_number] => 10090237 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-02 [patent_title] => Semiconductor device and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 15/727510 [patent_app_country] => US [patent_app_date] => 2017-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 10362 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 261 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15727510 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/727510
Semiconductor device and manufacturing method thereof Oct 5, 2017 Issued
Array ( [id] => 14137997 [patent_doc_number] => 20190103388 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-04 [patent_title] => PACKAGE ON PACKAGE WITH INTEGRATED PASSIVE ELECTRONICS METHOD AND APPARATUS [patent_app_type] => utility [patent_app_number] => 15/721057 [patent_app_country] => US [patent_app_date] => 2017-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7185 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15721057 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/721057
Package on package with integrated passive electronics method and apparatus Sep 28, 2017 Issued
Array ( [id] => 12516060 [patent_doc_number] => 10002821 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-06-19 [patent_title] => Semiconductor chip package comprising semiconductor chip and leadframe disposed between two substrates [patent_app_type] => utility [patent_app_number] => 15/720985 [patent_app_country] => US [patent_app_date] => 2017-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 8505 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 288 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15720985 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/720985
Semiconductor chip package comprising semiconductor chip and leadframe disposed between two substrates Sep 28, 2017 Issued
Array ( [id] => 16521622 [patent_doc_number] => 10872847 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-22 [patent_title] => Package structure and method for fabricating the same [patent_app_type] => utility [patent_app_number] => 15/720552 [patent_app_country] => US [patent_app_date] => 2017-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 2624 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15720552 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/720552
Package structure and method for fabricating the same Sep 28, 2017 Issued
Array ( [id] => 12800740 [patent_doc_number] => 20180158749 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-07 [patent_title] => Package Structure for Heat Dissipation [patent_app_type] => utility [patent_app_number] => 15/720565 [patent_app_country] => US [patent_app_date] => 2017-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16354 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15720565 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/720565
Package structure for heat dissipation Sep 28, 2017 Issued
Array ( [id] => 12236033 [patent_doc_number] => 20180068896 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-08 [patent_title] => 'METHOD OF FABRICATING ELECTRONIC PACKAGE' [patent_app_type] => utility [patent_app_number] => 15/704388 [patent_app_country] => US [patent_app_date] => 2017-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2958 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15704388 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/704388
Method of fabricating electronic package Sep 13, 2017 Issued
Array ( [id] => 14252643 [patent_doc_number] => 10276529 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-30 [patent_title] => Semiconductor devices including conductive pillars [patent_app_type] => utility [patent_app_number] => 15/687691 [patent_app_country] => US [patent_app_date] => 2017-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 6315 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15687691 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/687691
Semiconductor devices including conductive pillars Aug 27, 2017 Issued
Array ( [id] => 12990133 [patent_doc_number] => 20170345785 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-30 [patent_title] => Contact Area Design for Solder Bonding [patent_app_type] => utility [patent_app_number] => 15/682137 [patent_app_country] => US [patent_app_date] => 2017-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7214 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15682137 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/682137
Contact area design for solder bonding Aug 20, 2017 Issued
Array ( [id] => 15108873 [patent_doc_number] => 10475768 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-12 [patent_title] => Redistribution layers in semiconductor packages and methods of forming same [patent_app_type] => utility [patent_app_number] => 15/682261 [patent_app_country] => US [patent_app_date] => 2017-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 23 [patent_no_of_words] => 10377 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15682261 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/682261
Redistribution layers in semiconductor packages and methods of forming same Aug 20, 2017 Issued
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