Search

Sheila V. Clark

Examiner (ID: 256, Phone: (571)272-1725 , Office: P/2896 )

Most Active Art Unit
2815
Art Unit(s)
2503, 2823, 2815, 2607, 2504, 2891, 2508, 2896
Total Applications
3274
Issued Applications
2860
Pending Applications
49
Abandoned Applications
366

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15108887 [patent_doc_number] => 10475775 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-12 [patent_title] => Semiconductor package device and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 15/680063 [patent_app_country] => US [patent_app_date] => 2017-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 4599 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15680063 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/680063
Semiconductor package device and method of manufacturing the same Aug 16, 2017 Issued
Array ( [id] => 12692725 [patent_doc_number] => 20180122741 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-03 [patent_title] => SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 15/679662 [patent_app_country] => US [patent_app_date] => 2017-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5720 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15679662 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/679662
Semiconductor device and semiconductor package including the same Aug 16, 2017 Issued
Array ( [id] => 13963111 [patent_doc_number] => 20190057900 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-21 [patent_title] => THIN SEMICONDUCTOR PACKAGE AND RELATED METHODS [patent_app_type] => utility [patent_app_number] => 15/679664 [patent_app_country] => US [patent_app_date] => 2017-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5426 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15679664 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/679664
Thin semiconductor package and related methods Aug 16, 2017 Issued
Array ( [id] => 13667371 [patent_doc_number] => 10163864 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-12-25 [patent_title] => Vertically stacked wafers and methods of forming same [patent_app_type] => utility [patent_app_number] => 15/678642 [patent_app_country] => US [patent_app_date] => 2017-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 5891 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15678642 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/678642
Vertically stacked wafers and methods of forming same Aug 15, 2017 Issued
Array ( [id] => 13293225 [patent_doc_number] => 10157813 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-18 [patent_title] => 3DIC packaging with hot spot thermal management features [patent_app_type] => utility [patent_app_number] => 15/676963 [patent_app_country] => US [patent_app_date] => 2017-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 5216 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15676963 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/676963
3DIC packaging with hot spot thermal management features Aug 13, 2017 Issued
Array ( [id] => 13005951 [patent_doc_number] => 10026646 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-17 [patent_title] => Packages with through-vias having tapered ends [patent_app_type] => utility [patent_app_number] => 15/668315 [patent_app_country] => US [patent_app_date] => 2017-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 20 [patent_no_of_words] => 4539 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15668315 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/668315
Packages with through-vias having tapered ends Aug 2, 2017 Issued
Array ( [id] => 13754869 [patent_doc_number] => 10170386 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-01 [patent_title] => Electronic component package and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 15/667738 [patent_app_country] => US [patent_app_date] => 2017-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 27 [patent_no_of_words] => 12867 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15667738 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/667738
Electronic component package and method of manufacturing the same Aug 2, 2017 Issued
Array ( [id] => 12026944 [patent_doc_number] => 20170317043 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-02 [patent_title] => 'METHOD FOR WAFER DICING' [patent_app_type] => utility [patent_app_number] => 15/654512 [patent_app_country] => US [patent_app_date] => 2017-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 3342 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15654512 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/654512
Method for wafer dicing Jul 18, 2017 Issued
Array ( [id] => 12250093 [patent_doc_number] => 09922875 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-20 [patent_title] => 'Conductive interconnect structures incorporating negative thermal expansion materials and associated systems, devices, and methods' [patent_app_type] => utility [patent_app_number] => 15/653365 [patent_app_country] => US [patent_app_date] => 2017-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 4062 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15653365 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/653365
Conductive interconnect structures incorporating negative thermal expansion materials and associated systems, devices, and methods Jul 17, 2017 Issued
Array ( [id] => 13242983 [patent_doc_number] => 10134701 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-20 [patent_title] => Solder bump for ball grid array [patent_app_type] => utility [patent_app_number] => 15/651063 [patent_app_country] => US [patent_app_date] => 2017-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 2419 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15651063 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/651063
Solder bump for ball grid array Jul 16, 2017 Issued
Array ( [id] => 13257091 [patent_doc_number] => 10141239 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-27 [patent_title] => Thermal dissipation through seal rings in 3DIC structure [patent_app_type] => utility [patent_app_number] => 15/651810 [patent_app_country] => US [patent_app_date] => 2017-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4370 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15651810 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/651810
Thermal dissipation through seal rings in 3DIC structure Jul 16, 2017 Issued
Array ( [id] => 14672003 [patent_doc_number] => 10373921 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-06 [patent_title] => Power gate circuits for semiconductor devices [patent_app_type] => utility [patent_app_number] => 15/628343 [patent_app_country] => US [patent_app_date] => 2017-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 9510 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15628343 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/628343
Power gate circuits for semiconductor devices Jun 19, 2017 Issued
Array ( [id] => 13071107 [patent_doc_number] => 10056339 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-21 [patent_title] => Semiconductor devices [patent_app_type] => utility [patent_app_number] => 15/628349 [patent_app_country] => US [patent_app_date] => 2017-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 21 [patent_no_of_words] => 5292 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15628349 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/628349
Semiconductor devices Jun 19, 2017 Issued
Array ( [id] => 12615414 [patent_doc_number] => 20180096968 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-05 [patent_title] => FAN-OUT SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 15/627957 [patent_app_country] => US [patent_app_date] => 2017-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14378 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15627957 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/627957
Fan-out semiconductor package Jun 19, 2017 Issued
Array ( [id] => 14300817 [patent_doc_number] => 10290539 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-14 [patent_title] => Semiconductor interconnect structure and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 15/627961 [patent_app_country] => US [patent_app_date] => 2017-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3679 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15627961 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/627961
Semiconductor interconnect structure and manufacturing method thereof Jun 19, 2017 Issued
Array ( [id] => 12019723 [patent_doc_number] => 09812434 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-11-07 [patent_title] => 'Hollow metal pillar packaging scheme' [patent_app_type] => utility [patent_app_number] => 15/614096 [patent_app_country] => US [patent_app_date] => 2017-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 2763 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15614096 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/614096
Hollow metal pillar packaging scheme Jun 4, 2017 Issued
Array ( [id] => 14333015 [patent_doc_number] => 10297536 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-21 [patent_title] => Direct selective adhesion promotor plating [patent_app_type] => utility [patent_app_number] => 15/605093 [patent_app_country] => US [patent_app_date] => 2017-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6464 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15605093 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/605093
Direct selective adhesion promotor plating May 24, 2017 Issued
Array ( [id] => 12434028 [patent_doc_number] => 09977857 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-05-22 [patent_title] => Method and circuit for via pillar optimization [patent_app_type] => utility [patent_app_number] => 15/600410 [patent_app_country] => US [patent_app_date] => 2017-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4427 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15600410 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/600410
Method and circuit for via pillar optimization May 18, 2017 Issued
Array ( [id] => 12061820 [patent_doc_number] => 20170338164 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-23 [patent_title] => 'CHIP PACKAGE AND METHOD OF FORMING A CHIP PACKAGE' [patent_app_type] => utility [patent_app_number] => 15/599492 [patent_app_country] => US [patent_app_date] => 2017-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 12478 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15599492 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/599492
Chip package and method of forming a chip package May 18, 2017 Issued
Array ( [id] => 13257161 [patent_doc_number] => 10141276 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-27 [patent_title] => Semiconductor package structure and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 15/599481 [patent_app_country] => US [patent_app_date] => 2017-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 33 [patent_no_of_words] => 6445 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15599481 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/599481
Semiconductor package structure and manufacturing method thereof May 18, 2017 Issued
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