Search

Shelly A. Chase

Examiner (ID: 3566, Phone: (571)272-3816 , Office: P/2112 )

Most Active Art Unit
2112
Art Unit(s)
2784, 2786, 2133, 2112
Total Applications
2020
Issued Applications
1860
Pending Applications
102
Abandoned Applications
74

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20053448 [patent_doc_number] => 20250191670 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-12 [patent_title] => BLOCK FAMILY ERROR AVOIDANCE BIN DESIGNS ADDRESSING ERROR CORRECTION DECODER THROUGHPUT SPECIFICATIONS [patent_app_type] => utility [patent_app_number] => 19/053165 [patent_app_country] => US [patent_app_date] => 2025-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7116 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19053165 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/053165
BLOCK FAMILY ERROR AVOIDANCE BIN DESIGNS ADDRESSING ERROR CORRECTION DECODER THROUGHPUT SPECIFICATIONS Feb 12, 2025 Pending
Array ( [id] => 20281826 [patent_doc_number] => 20250307068 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-02 [patent_title] => MULTI-PROTOCOL SUPPORT ON COMMON PHYSICAL LAYER [patent_app_type] => utility [patent_app_number] => 19/048585 [patent_app_country] => US [patent_app_date] => 2025-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12026 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19048585 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/048585
MULTI-PROTOCOL SUPPORT ON COMMON PHYSICAL LAYER Feb 6, 2025 Pending
Array ( [id] => 20029698 [patent_doc_number] => 20250167920 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-22 [patent_title] => COMMUNICATION TECHNIQUES APPLYING LOW-DENSITY PARITY-CHECK CODE BASE GRAPH SELECTION [patent_app_type] => utility [patent_app_number] => 19/033823 [patent_app_country] => US [patent_app_date] => 2025-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13091 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19033823 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/033823
COMMUNICATION TECHNIQUES APPLYING LOW-DENSITY PARITY-CHECK CODE BASE GRAPH SELECTION Jan 21, 2025 Pending
Array ( [id] => 20502471 [patent_doc_number] => 20260031934 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-29 [patent_title] => MODEM CHIP CAPABLE OF PERFORMING CYCLIC REDUNDANCY CHECK USING INTERNAL MEMORY AND SYSTEM ON CHIP INCLUDING THE MODEM CHIP [patent_app_type] => utility [patent_app_number] => 19/030230 [patent_app_country] => US [patent_app_date] => 2025-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12181 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19030230 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/030230
MODEM CHIP CAPABLE OF PERFORMING CYCLIC REDUNDANCY CHECK USING INTERNAL MEMORY AND SYSTEM ON CHIP INCLUDING THE MODEM CHIP Jan 16, 2025 Pending
Array ( [id] => 20138039 [patent_doc_number] => 20250245083 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-31 [patent_title] => CONTROLLER THAT RECEIVES A CYCLIC REDUNDANCY CHECK (CRC) CODE FOR BOTH READ AND WRITE DATA TRANSMITTED VIA BIDIRECTIONAL DATA LINK [patent_app_type] => utility [patent_app_number] => 19/017200 [patent_app_country] => US [patent_app_date] => 2025-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5612 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19017200 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/017200
CONTROLLER THAT RECEIVES A CYCLIC REDUNDANCY CHECK (CRC) CODE FOR BOTH READ AND WRITE DATA TRANSMITTED VIA BIDIRECTIONAL DATA LINK Jan 9, 2025 Pending
Array ( [id] => 20003370 [patent_doc_number] => 20250141592 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-01 [patent_title] => FORWARD ERROR CORRECTION BYPASS FOR REDUCED POWER [patent_app_type] => utility [patent_app_number] => 19/004057 [patent_app_country] => US [patent_app_date] => 2024-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19004057 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/004057
FORWARD ERROR CORRECTION BYPASS FOR REDUCED POWER Dec 26, 2024 Pending
Array ( [id] => 20089830 [patent_doc_number] => 20250219766 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-03 [patent_title] => Initial Control Frame Design with Per-User Frame Check Sequence [patent_app_type] => utility [patent_app_number] => 18/991265 [patent_app_country] => US [patent_app_date] => 2024-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6164 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18991265 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/991265
Initial Control Frame Design with Per-User Frame Check Sequence Dec 19, 2024 Pending
Array ( [id] => 20063106 [patent_doc_number] => 20250201328 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-19 [patent_title] => DRAM RETENTION TEST METHOD FOR DYNAMIC ERROR CORRECTION [patent_app_type] => utility [patent_app_number] => 18/990627 [patent_app_country] => US [patent_app_date] => 2024-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15376 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18990627 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/990627
DRAM RETENTION TEST METHOD FOR DYNAMIC ERROR CORRECTION Dec 19, 2024 Pending
Array ( [id] => 20029696 [patent_doc_number] => 20250167918 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-22 [patent_title] => METHOD FOR POLAR CODING AND APPARATUS [patent_app_type] => utility [patent_app_number] => 18/988086 [patent_app_country] => US [patent_app_date] => 2024-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13539 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18988086 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/988086
METHOD FOR POLAR CODING AND APPARATUS Dec 18, 2024 Pending
Array ( [id] => 20045692 [patent_doc_number] => 20250183914 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-05 [patent_title] => APPARATUS AND METHOD FOR CHANNEL CODING IN COMMUNICATION SYSTEM [patent_app_type] => utility [patent_app_number] => 18/977898 [patent_app_country] => US [patent_app_date] => 2024-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19177 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18977898 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/977898
APPARATUS AND METHOD FOR CHANNEL CODING IN COMMUNICATION SYSTEM Dec 10, 2024 Pending
Array ( [id] => 20421873 [patent_doc_number] => 20250383958 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-18 [patent_title] => MEMORY SYSTEM, MEMORY CONTROLLER, AND METHOD OF CONTROLLING NONVOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 18/974157 [patent_app_country] => US [patent_app_date] => 2024-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8519 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18974157 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/974157
MEMORY SYSTEM, MEMORY CONTROLLER, AND METHOD OF CONTROLLING NONVOLATILE MEMORY Dec 8, 2024 Pending
Array ( [id] => 19848063 [patent_doc_number] => 20250093414 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-20 [patent_title] => APPARATUS FOR TESTING A DEVICE UNDER TEST SEPARATING ERRORS WITHIN A RECEIVED PATTERN ASSOCIATED WITH DIFFERENT FUNCTIONAL BLOCKS OF A DEVICE UNDER TEST OR ASSOCIATED WITH DIFFERENT BLOCKS OF ONE OR MORE BITS, METHOD AND COMPUTER PROGRAM [patent_app_type] => utility [patent_app_number] => 18/971433 [patent_app_country] => US [patent_app_date] => 2024-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26845 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18971433 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/971433
APPARATUS FOR TESTING A DEVICE UNDER TEST SEPARATING ERRORS WITHIN A RECEIVED PATTERN ASSOCIATED WITH DIFFERENT FUNCTIONAL BLOCKS OF A DEVICE UNDER TEST OR ASSOCIATED WITH DIFFERENT BLOCKS OF ONE OR MORE BITS, METHOD AND COMPUTER PROGRAM Dec 5, 2024 Pending
Array ( [id] => 20063104 [patent_doc_number] => 20250201326 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-19 [patent_title] => DIE-LEVEL BLOCK FAMILY ERROR AVOIDANCE [patent_app_type] => utility [patent_app_number] => 18/967199 [patent_app_country] => US [patent_app_date] => 2024-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10738 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18967199 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/967199
DIE-LEVEL BLOCK FAMILY ERROR AVOIDANCE Dec 2, 2024 Pending
Array ( [id] => 20500634 [patent_doc_number] => 20260030094 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-29 [patent_title] => DECODER, DECODING METHOD, MEMORY SYSTEM AND CONTROLLER [patent_app_type] => utility [patent_app_number] => 18/965734 [patent_app_country] => US [patent_app_date] => 2024-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6202 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18965734 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/965734
DECODER, DECODING METHOD, MEMORY SYSTEM AND CONTROLLER Dec 1, 2024 Pending
Array ( [id] => 19802592 [patent_doc_number] => 20250068517 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-27 [patent_title] => STORAGE DEVICE INCLUDING MAPPING MEMORY AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/944088 [patent_app_country] => US [patent_app_date] => 2024-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11662 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18944088 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/944088
STORAGE DEVICE INCLUDING MAPPING MEMORY AND METHOD OF OPERATING THE SAME Nov 11, 2024 Pending
Array ( [id] => 19987572 [patent_doc_number] => 20250125794 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-17 [patent_title] => SYSTEM AND METHOD FOR PULSE GENERATION DURING QUANTUM OPERATIONS [patent_app_type] => utility [patent_app_number] => 18/928277 [patent_app_country] => US [patent_app_date] => 2024-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18928277 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/928277
SYSTEM AND METHOD FOR PULSE GENERATION DURING QUANTUM OPERATIONS Oct 27, 2024 Pending
Array ( [id] => 20429320 [patent_doc_number] => 20250391413 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-25 [patent_title] => METHOD AND SYSTEM FOR CONCEALING PACKET LOSS IN A COMMUNICATION SYSTEM [patent_app_type] => utility [patent_app_number] => 18/926782 [patent_app_country] => US [patent_app_date] => 2024-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4639 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18926782 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/926782
METHOD AND SYSTEM FOR CONCEALING PACKET LOSS IN A COMMUNICATION SYSTEM Oct 24, 2024 Pending
Array ( [id] => 19774169 [patent_doc_number] => 20250055595 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-13 [patent_title] => METHODS AND APPARATUS FOR INFORMATION TRANSMISSION [patent_app_type] => utility [patent_app_number] => 18/926197 [patent_app_country] => US [patent_app_date] => 2024-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 44904 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18926197 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/926197
METHODS AND APPARATUS FOR INFORMATION TRANSMISSION Oct 23, 2024 Pending
Array ( [id] => 20086516 [patent_doc_number] => 20250216452 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-03 [patent_title] => DEVICE TESTING SYSTEM AND DEVICE TESTING METHOD [patent_app_type] => utility [patent_app_number] => 18/908945 [patent_app_country] => US [patent_app_date] => 2024-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18908945 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/908945
DEVICE TESTING SYSTEM AND DEVICE TESTING METHOD Oct 7, 2024 Pending
Array ( [id] => 20036975 [patent_doc_number] => 20250175197 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-29 [patent_title] => SIGNAL TRANSMITTING METHOD, ELECTRONIC DEVICE, AND COMMUNICATION SYSTEM [patent_app_type] => utility [patent_app_number] => 18/898590 [patent_app_country] => US [patent_app_date] => 2024-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18898590 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/898590
Signal transmitting method, electronic device, and communication system Sep 25, 2024 Issued
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