Shelly A. Chase

Array ( [id] => 5949066 [patent_doc_number] => 20110107191 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-05 [patent_title] => 'Method of detecting error in a semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 12/929250 [patent_app_country] => US [patent_app_date] => 2011-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 12172 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0107/20110107191.pdf [firstpage_image] =>[orig_patent_app_number] => 12929250 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8536169 [patent_doc_number] => 08312334 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-13 [patent_title] => 'Semiconductor test apparatus' [patent_app_type] => utility [patent_app_number] => 12/986544 [patent_app_country] => US [patent_app_date] => 2011-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 7138 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12986544 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6147471 [patent_doc_number] => 20110131469 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-02 [patent_title] => 'METHOD, DEVICE AND APPARATUS FOR CORRECTING BURSTS' [patent_app_type] => utility [patent_app_number] => 12/982617 [patent_app_country] => US [patent_app_date] => 2010-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6629 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0131/20110131469.pdf [firstpage_image] =>[orig_patent_app_number] => 12982617 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7718703 [patent_doc_number] => 08095863 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-10 [patent_title] => 'Low complexity decoding of low density parity check codes' [patent_app_type] => utility [patent_app_number] => 12/963321 [patent_app_country] => US [patent_app_date] => 2010-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 6170 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/095/08095863.pdf [firstpage_image] =>[orig_patent_app_number] => 12963321 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8580962 [patent_doc_number] => 08347193 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-01 [patent_title] => 'Parallel inversionless error and erasure processing' [patent_app_type] => utility [patent_app_number] => 12/960094 [patent_app_country] => US [patent_app_date] => 2010-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4010 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12960094 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6147489 [patent_doc_number] => 20110131476 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-02 [patent_title] => 'RECORDING APPARATUS AND RECORDING METHOD' [patent_app_type] => utility [patent_app_number] => 12/957440 [patent_app_country] => US [patent_app_date] => 2010-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 39 [patent_no_of_words] => 18031 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0131/20110131476.pdf [firstpage_image] =>[orig_patent_app_number] => 12957440 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6147478 [patent_doc_number] => 20110131475 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-02 [patent_title] => 'METHOD FOR DETERMINING A COPY TO BE DECODED AND AN ASSOCIATED ERASURES VECTOR, CORRESPONDING STORAGE MEANS AND RECEIVER DEVICE' [patent_app_type] => utility [patent_app_number] => 12/957707 [patent_app_country] => US [patent_app_date] => 2010-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11229 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0131/20110131475.pdf [firstpage_image] =>[orig_patent_app_number] => 12957707 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8580952 [patent_doc_number] => 08347184 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-01 [patent_title] => 'Cloud storage data access method, apparatus and system' [patent_app_type] => utility [patent_app_number] => 13/000575 [patent_app_country] => US [patent_app_date] => 2010-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4204 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13000575 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9187176 [patent_doc_number] => 08627176 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-07 [patent_title] => 'Systematic mitigation of memory errors' [patent_app_type] => utility [patent_app_number] => 12/956342 [patent_app_country] => US [patent_app_date] => 2010-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6945 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12956342 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5981925 [patent_doc_number] => 20110072336 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-24 [patent_title] => 'LDPC (Low Density Parity Check) coded modulation symbol decoding' [patent_app_type] => utility [patent_app_number] => 12/957238 [patent_app_country] => US [patent_app_date] => 2010-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 18125 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20110072336.pdf [firstpage_image] =>[orig_patent_app_number] => 12957238 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8222988 [patent_doc_number] => 20120137194 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-31 [patent_title] => 'Forward Error Correction with Configurable Latency' [patent_app_type] => utility [patent_app_number] => 12/954784 [patent_app_country] => US [patent_app_date] => 2010-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1079 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12954784 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5976753 [patent_doc_number] => 20110154166 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-23 [patent_title] => 'AUTHENTICATION MODULE, ELECTRIC DEVICE, AND INTERLEAVED SIGNAL RESTORING METHOD' [patent_app_type] => utility [patent_app_number] => 12/950331 [patent_app_country] => US [patent_app_date] => 2010-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8961 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0154/20110154166.pdf [firstpage_image] =>[orig_patent_app_number] => 12950331 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8672513 [patent_doc_number] => 20130047051 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-21 [patent_title] => 'HARQ PROCEDURE WITH PROCESSING OF STORED SOFT-BITS' [patent_app_type] => utility [patent_app_number] => 13/511565 [patent_app_country] => US [patent_app_date] => 2010-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 7817 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13511565 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8176786 [patent_doc_number] => 20120110418 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-03 [patent_title] => 'Advanced Data Encoding With Reduced Erasure Count For Solid State Drives' [patent_app_type] => utility [patent_app_number] => 13/059808 [patent_app_country] => US [patent_app_date] => 2010-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8971 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0110/20120110418.pdf [firstpage_image] =>[orig_patent_app_number] => 13059808 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5956948 [patent_doc_number] => 20110035648 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-02-10 [patent_title] => 'DTV TRANSMITTER AND METHOD OF CODING MAIN AND ENHANCED DATA IN DTV TRANSMITTER' [patent_app_type] => utility [patent_app_number] => 12/907881 [patent_app_country] => US [patent_app_date] => 2010-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8867 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0035/20110035648.pdf [firstpage_image] =>[orig_patent_app_number] => 12907881 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7819942 [patent_doc_number] => 20120066562 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-15 [patent_title] => 'INCREASING HYBRID AUTOMATIC REPEAT REQUEST (HARQ) THROUGHPUT' [patent_app_type] => utility [patent_app_number] => 12/881836 [patent_app_country] => US [patent_app_date] => 2010-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3844 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20120066562.pdf [firstpage_image] =>[orig_patent_app_number] => 12881836 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8787110 [patent_doc_number] => 08433965 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-30 [patent_title] => 'Method and apparatus for obtaining coefficients of a fractionally-spaced equalizer' [patent_app_type] => utility [patent_app_number] => 12/880740 [patent_app_country] => US [patent_app_date] => 2010-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8337 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 14 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12880740 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6204131 [patent_doc_number] => 20110066917 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-17 [patent_title] => 'Method and Apparatus for Elementary Updating a Check Node During Decoding of a Block Encoded with a Non-binary LDPC Code' [patent_app_type] => utility [patent_app_number] => 12/880844 [patent_app_country] => US [patent_app_date] => 2010-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7265 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20110066917.pdf [firstpage_image] =>[orig_patent_app_number] => 12880844 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7819939 [patent_doc_number] => 20120066559 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-15 [patent_title] => 'Built-in Bit Error Rate Test Circuit' [patent_app_type] => utility [patent_app_number] => 12/880960 [patent_app_country] => US [patent_app_date] => 2010-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4723 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20120066559.pdf [firstpage_image] =>[orig_patent_app_number] => 12880960 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5976709 [patent_doc_number] => 20110154138 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-23 [patent_title] => 'FAILURE ANALYSIS METHOD, FAILURE ANALYSIS APPARATUS, AND COMPUTER PROGRAM PRODUCT' [patent_app_type] => utility [patent_app_number] => 12/878247 [patent_app_country] => US [patent_app_date] => 2010-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8060 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0154/20110154138.pdf [firstpage_image] =>[orig_patent_app_number] => 12878247 [rel_patent_id] =>[rel_patent_doc_number] =>)