Search

Shelly A. Chase

Examiner (ID: 12402, Phone: (571)272-3816 , Office: P/2112 )

Most Active Art Unit
2112
Art Unit(s)
2786, 2112, 2784, 2133
Total Applications
2023
Issued Applications
1860
Pending Applications
105
Abandoned Applications
74

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20265848 [patent_doc_number] => 12436840 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-07 [patent_title] => Electronic device comprising a bluetooth communication unit [patent_app_type] => utility [patent_app_number] => 18/544732 [patent_app_country] => US [patent_app_date] => 2023-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 0 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18544732 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/544732
Electronic device comprising a bluetooth communication unit Dec 18, 2023 Issued
Array ( [id] => 19117313 [patent_doc_number] => 20240129063 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-18 [patent_title] => METHODS AND PROCEDURES FOR POLAR ENCODING AND DECODING WITH LOW LATENCY [patent_app_type] => utility [patent_app_number] => 18/543828 [patent_app_country] => US [patent_app_date] => 2023-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12608 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18543828 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/543828
Methods and procedures for polar encoding and decoding with low latency Dec 17, 2023 Issued
Array ( [id] => 19822063 [patent_doc_number] => 20250080270 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => APPLICATION-LEVEL FORWARD ERROR CORRECTION TECHNIQUES [patent_app_type] => utility [patent_app_number] => 18/538444 [patent_app_country] => US [patent_app_date] => 2023-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8961 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18538444 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/538444
Application-level forward error correction techniques Dec 12, 2023 Issued
Array ( [id] => 20375904 [patent_doc_number] => 12483351 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-25 [patent_title] => Code block segmentation and configuration for concatenated turbo and RS coding [patent_app_type] => utility [patent_app_number] => 18/527738 [patent_app_country] => US [patent_app_date] => 2023-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3747 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18527738 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/527738
Code block segmentation and configuration for concatenated turbo and RS coding Dec 3, 2023 Issued
Array ( [id] => 19253807 [patent_doc_number] => 20240204804 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => DATA PROCESSING SYSTEM AND DATA PROCESSING METHOD FOR DEEP NEURAL NETWORK MODEL [patent_app_type] => utility [patent_app_number] => 18/522242 [patent_app_country] => US [patent_app_date] => 2023-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4682 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18522242 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/522242
Data processing system and data processing method for deep neural network model Nov 28, 2023 Issued
Array ( [id] => 19037830 [patent_doc_number] => 20240087645 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-14 [patent_title] => STRESSING ALGORITHM FOR SOLVING CELL-TO-CELL VARIATIONS IN PHASE CHANGE MEMORY [patent_app_type] => utility [patent_app_number] => 18/516733 [patent_app_country] => US [patent_app_date] => 2023-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5766 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18516733 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/516733
Stressing algorithm for solving cell-to-cell variations in phase change memory Nov 20, 2023 Issued
Array ( [id] => 19192394 [patent_doc_number] => 20240171307 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-23 [patent_title] => METHOD FOR POLAR CODING AND APPARATUS [patent_app_type] => utility [patent_app_number] => 18/512912 [patent_app_country] => US [patent_app_date] => 2023-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18082 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18512912 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/512912
Method for polar coding and apparatus Nov 16, 2023 Issued
Array ( [id] => 19720126 [patent_doc_number] => 12205669 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-21 [patent_title] => Memory buffer with data scrambling and error correction [patent_app_type] => utility [patent_app_number] => 18/513473 [patent_app_country] => US [patent_app_date] => 2023-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 27 [patent_no_of_words] => 7256 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18513473 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/513473
Memory buffer with data scrambling and error correction Nov 16, 2023 Issued
Array ( [id] => 19926960 [patent_doc_number] => 12301260 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-05-13 [patent_title] => Systems and methods for generating optimized combination sets for error correction in data transmission [patent_app_type] => utility [patent_app_number] => 18/507765 [patent_app_country] => US [patent_app_date] => 2023-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 8134 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18507765 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/507765
Systems and methods for generating optimized combination sets for error correction in data transmission Nov 12, 2023 Issued
Array ( [id] => 20011983 [patent_doc_number] => 20250150205 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-08 [patent_title] => MODULATION OF EXTENDED LONG RANGE WIRELESS PACKETS [patent_app_type] => utility [patent_app_number] => 18/502880 [patent_app_country] => US [patent_app_date] => 2023-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18683 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18502880 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/502880
Modulation of extended long range wireless packets Nov 5, 2023 Issued
Array ( [id] => 19214243 [patent_doc_number] => 12003323 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-04 [patent_title] => AI model with error-detection code for fault correction in 5G/6G [patent_app_type] => utility [patent_app_number] => 18/502054 [patent_app_country] => US [patent_app_date] => 2023-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 38 [patent_no_of_words] => 24949 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18502054 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/502054
AI model with error-detection code for fault correction in 5G/6G Nov 4, 2023 Issued
Array ( [id] => 20011979 [patent_doc_number] => 20250150201 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-08 [patent_title] => Method for Link Transition in Universal Serial Bus and System Thereof [patent_app_type] => utility [patent_app_number] => 18/501050 [patent_app_country] => US [patent_app_date] => 2023-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18501050 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/501050
Method for link transition in universal serial bus and system thereof Nov 2, 2023 Issued
Array ( [id] => 20333461 [patent_doc_number] => 12463749 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-04 [patent_title] => Method and apparatus for generating error correcting codes with transition encoding [patent_app_type] => utility [patent_app_number] => 18/478505 [patent_app_country] => US [patent_app_date] => 2023-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 1174 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18478505 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/478505
Method and apparatus for generating error correcting codes with transition encoding Oct 26, 2023 Issued
Array ( [id] => 19766550 [patent_doc_number] => 12224858 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-11 [patent_title] => Data sending and receiving method and device [patent_app_type] => utility [patent_app_number] => 18/488864 [patent_app_country] => US [patent_app_date] => 2023-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 16595 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18488864 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/488864
Data sending and receiving method and device Oct 16, 2023 Issued
Array ( [id] => 19024541 [patent_doc_number] => 20240080712 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-07 [patent_title] => Fault Mitigation Using Signal Quality and Error-Detection Codes in 5G/6G [patent_app_type] => utility [patent_app_number] => 18/488791 [patent_app_country] => US [patent_app_date] => 2023-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23613 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18488791 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/488791
Fault mitigation using signal quality and error-detection codes in 5G/6G Oct 16, 2023 Issued
Array ( [id] => 19147394 [patent_doc_number] => 20240146460 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-02 [patent_title] => Method for Code Block Group Based Channel Quality Indicator Calculations [patent_app_type] => utility [patent_app_number] => 18/486311 [patent_app_country] => US [patent_app_date] => 2023-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11133 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18486311 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/486311
Method for Code Block Group Based Channel Quality Indicator Calculations Oct 12, 2023 Abandoned
Array ( [id] => 19189176 [patent_doc_number] => 20240168089 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-23 [patent_title] => SEMICONDUCTOR DEVICE, DEBUG SYSTEM, AND DEBUG METHOD [patent_app_type] => utility [patent_app_number] => 18/483714 [patent_app_country] => US [patent_app_date] => 2023-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7054 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 328 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18483714 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/483714
Semiconductor device, debug system, and debug method Oct 9, 2023 Issued
Array ( [id] => 19286827 [patent_doc_number] => 20240223307 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => PARALLEL SELECTION OF FIFTH GENERATION (5G) NEW RADIO INFORMATION [patent_app_type] => utility [patent_app_number] => 18/377605 [patent_app_country] => US [patent_app_date] => 2023-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 84254 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -29 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18377605 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/377605
Parallel selection of fifth generation (5G) new radio information Oct 5, 2023 Issued
Array ( [id] => 19460664 [patent_doc_number] => 12101184 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-24 [patent_title] => Method and system for reducing data stored in capture buffer [patent_app_type] => utility [patent_app_number] => 18/374900 [patent_app_country] => US [patent_app_date] => 2023-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 29 [patent_no_of_words] => 33976 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18374900 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/374900
Method and system for reducing data stored in capture buffer Sep 28, 2023 Issued
Array ( [id] => 19863788 [patent_doc_number] => 20250102574 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-27 [patent_title] => TEST TIME REDUCTION IN CIRCUITS WITH REDUNDANCY FLIP-FLOPS [patent_app_type] => utility [patent_app_number] => 18/474511 [patent_app_country] => US [patent_app_date] => 2023-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9527 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18474511 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/474511
Test time reduction in circuits with redundancy flip-flops Sep 25, 2023 Issued
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