Search

Shelly A. Chase

Examiner (ID: 3566, Phone: (571)272-3816 , Office: P/2112 )

Most Active Art Unit
2112
Art Unit(s)
2784, 2786, 2133, 2112
Total Applications
2020
Issued Applications
1860
Pending Applications
102
Abandoned Applications
74

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4923809 [patent_doc_number] => 20080072126 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-20 [patent_title] => 'PROGRAMMABLE TRELLIS DECODER AND ASSOCIATED METHODS' [patent_app_type] => utility [patent_app_number] => 11/531462 [patent_app_country] => US [patent_app_date] => 2006-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4638 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20080072126.pdf [firstpage_image] =>[orig_patent_app_number] => 11531462 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/531462
Programmable trellis decoder and associated methods Sep 12, 2006 Issued
Array ( [id] => 163453 [patent_doc_number] => 07676736 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-09 [patent_title] => 'Programmable continuous phase modulation (CPM) decoder and associated methods' [patent_app_type] => utility [patent_app_number] => 11/531447 [patent_app_country] => US [patent_app_date] => 2006-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4416 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/676/07676736.pdf [firstpage_image] =>[orig_patent_app_number] => 11531447 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/531447
Programmable continuous phase modulation (CPM) decoder and associated methods Sep 12, 2006 Issued
Array ( [id] => 4706443 [patent_doc_number] => 20080065967 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-13 [patent_title] => 'System for controlling high-speed bidirectional communication' [patent_app_type] => utility [patent_app_number] => 11/518843 [patent_app_country] => US [patent_app_date] => 2006-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4683 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0065/20080065967.pdf [firstpage_image] =>[orig_patent_app_number] => 11518843 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/518843
System for controlling high-speed bidirectional communication Sep 10, 2006 Issued
Array ( [id] => 69108 [patent_doc_number] => 07761777 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-20 [patent_title] => 'Soft decision demapping method suitable for higher-order modulation for iterative decoder and error correction apparatus using the same' [patent_app_type] => utility [patent_app_number] => 11/518247 [patent_app_country] => US [patent_app_date] => 2006-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 5308 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/761/07761777.pdf [firstpage_image] =>[orig_patent_app_number] => 11518247 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/518247
Soft decision demapping method suitable for higher-order modulation for iterative decoder and error correction apparatus using the same Sep 10, 2006 Issued
Array ( [id] => 5137585 [patent_doc_number] => 20070079214 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-05 [patent_title] => 'Apparatus and method for processing data of an optical disk' [patent_app_type] => utility [patent_app_number] => 11/518234 [patent_app_country] => US [patent_app_date] => 2006-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4978 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0079/20070079214.pdf [firstpage_image] =>[orig_patent_app_number] => 11518234 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/518234
Apparatus and method for processing data of an optical disk Sep 10, 2006 Issued
Array ( [id] => 4447622 [patent_doc_number] => 07930623 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-19 [patent_title] => 'Method and system for generating parallel codes' [patent_app_type] => utility [patent_app_number] => 11/517985 [patent_app_country] => US [patent_app_date] => 2006-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 8036 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/930/07930623.pdf [firstpage_image] =>[orig_patent_app_number] => 11517985 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/517985
Method and system for generating parallel codes Sep 7, 2006 Issued
Array ( [id] => 5137553 [patent_doc_number] => 20070079182 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-05 [patent_title] => 'METHOD FOR CALCULATING AN ERROR DETECTING CODE' [patent_app_type] => utility [patent_app_number] => 11/530034 [patent_app_country] => US [patent_app_date] => 2006-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7207 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0079/20070079182.pdf [firstpage_image] =>[orig_patent_app_number] => 11530034 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/530034
Method for calculating an error detecting code Sep 7, 2006 Issued
Array ( [id] => 4984461 [patent_doc_number] => 20070089020 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-19 [patent_title] => 'BLOCK PROCESSING IN A BLOCK DECODING DEVICE' [patent_app_type] => utility [patent_app_number] => 11/470982 [patent_app_country] => US [patent_app_date] => 2006-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6489 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0089/20070089020.pdf [firstpage_image] =>[orig_patent_app_number] => 11470982 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/470982
Block processing in a block decoding device Sep 6, 2006 Issued
Array ( [id] => 336890 [patent_doc_number] => 07509565 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-24 [patent_title] => 'Wireless access modem having downstream channel resynchronization method' [patent_app_type] => utility [patent_app_number] => 11/470916 [patent_app_country] => US [patent_app_date] => 2006-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4604 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/509/07509565.pdf [firstpage_image] =>[orig_patent_app_number] => 11470916 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/470916
Wireless access modem having downstream channel resynchronization method Sep 6, 2006 Issued
Array ( [id] => 4923807 [patent_doc_number] => 20080072124 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-20 [patent_title] => 'APPARATUS AND METHOD FOR DETECTING PUNCTURE POSITION IN A SYMBOL STREAM ENCODED BY PUNCTURED CONVOLUTIONAL CODING SCHEME' [patent_app_type] => utility [patent_app_number] => 11/469911 [patent_app_country] => US [patent_app_date] => 2006-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3878 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20080072124.pdf [firstpage_image] =>[orig_patent_app_number] => 11469911 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/469911
Apparatus and method for detecting puncture position in a symbol stream encoded by punctured convolutional coding scheme Sep 4, 2006 Issued
Array ( [id] => 5184551 [patent_doc_number] => 20070055905 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-08 [patent_title] => 'Parity engine for use in storage virtualization controller and method of generating data by parity engine' [patent_app_type] => utility [patent_app_number] => 11/514159 [patent_app_country] => US [patent_app_date] => 2006-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 16375 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20070055905.pdf [firstpage_image] =>[orig_patent_app_number] => 11514159 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/514159
Parity engine for use in storage virtualization controller and method of generating data by parity engine Aug 31, 2006 Issued
Array ( [id] => 4995835 [patent_doc_number] => 20070011180 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-11 [patent_title] => 'SYSTEMS AND METHODS FOR ENHANCED STORED DATA VERIFICATION UTILIZING PAGEABLE POOL MEMORY' [patent_app_type] => utility [patent_app_number] => 11/469156 [patent_app_country] => US [patent_app_date] => 2006-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 10743 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0011/20070011180.pdf [firstpage_image] =>[orig_patent_app_number] => 11469156 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/469156
Systems and methods for enhanced stored data verification utilizing pageable pool memory Aug 30, 2006 Issued
Array ( [id] => 4546859 [patent_doc_number] => RE041992 [patent_country] => US [patent_kind] => E1 [patent_issue_date] => 2010-12-07 [patent_title] => 'Methods and circuitry for built-in self-testing of content addressable memories' [patent_app_type] => reissue [patent_app_number] => 11/514286 [patent_app_country] => US [patent_app_date] => 2006-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 30 [patent_no_of_words] => 9090 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/041/RE041992.pdf [firstpage_image] =>[orig_patent_app_number] => 11514286 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/514286
Methods and circuitry for built-in self-testing of content addressable memories Aug 29, 2006 Issued
Array ( [id] => 4923800 [patent_doc_number] => 20080072117 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-20 [patent_title] => 'PROGRAMMING A MEMORY DEVICE HAVING ERROR CORRECTION LOGIC' [patent_app_type] => utility [patent_app_number] => 11/468638 [patent_app_country] => US [patent_app_date] => 2006-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4322 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20080072117.pdf [firstpage_image] =>[orig_patent_app_number] => 11468638 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/468638
Programming a memory device having error correction logic Aug 29, 2006 Issued
Array ( [id] => 5058765 [patent_doc_number] => 20070061687 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-15 [patent_title] => 'Soft decoding method and apparatus, error correction method and apparatus, and soft output method and apparatus' [patent_app_type] => utility [patent_app_number] => 11/512365 [patent_app_country] => US [patent_app_date] => 2006-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 9410 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20070061687.pdf [firstpage_image] =>[orig_patent_app_number] => 11512365 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/512365
Soft decoding method and apparatus, error correction method and apparatus, and soft output method and apparatus Aug 29, 2006 Abandoned
Array ( [id] => 5255187 [patent_doc_number] => 20070136643 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-14 [patent_title] => 'Digital television transmitter/receiver and method of processing data in digital television transmitter/receiver' [patent_app_type] => utility [patent_app_number] => 11/514124 [patent_app_country] => US [patent_app_date] => 2006-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7033 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0136/20070136643.pdf [firstpage_image] =>[orig_patent_app_number] => 11514124 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/514124
Digital television transmitter/receiver and method of processing data in digital television transmitter/receiver Aug 29, 2006 Issued
Array ( [id] => 4732543 [patent_doc_number] => 20080049522 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-28 [patent_title] => 'CONTENT ADDRESSABLE MEMORY ENTRY CODING FOR ERROR DETECTION AND CORRECTION' [patent_app_type] => utility [patent_app_number] => 11/467097 [patent_app_country] => US [patent_app_date] => 2006-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 11616 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0049/20080049522.pdf [firstpage_image] =>[orig_patent_app_number] => 11467097 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/467097
Content addressable memory entry coding for error detection and correction Aug 23, 2006 Issued
Array ( [id] => 4735618 [patent_doc_number] => 20080052600 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-28 [patent_title] => 'Data corruption avoidance in DRAM chip sparing' [patent_app_type] => utility [patent_app_number] => 11/508758 [patent_app_country] => US [patent_app_date] => 2006-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4343 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20080052600.pdf [firstpage_image] =>[orig_patent_app_number] => 11508758 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/508758
Data corruption avoidance in DRAM chip sparing Aug 22, 2006 Issued
Array ( [id] => 118374 [patent_doc_number] => 07716561 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-11 [patent_title] => 'Multi-threshold reliability decoding of low-density parity check codes' [patent_app_type] => utility [patent_app_number] => 11/466292 [patent_app_country] => US [patent_app_date] => 2006-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 12497 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/716/07716561.pdf [firstpage_image] =>[orig_patent_app_number] => 11466292 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/466292
Multi-threshold reliability decoding of low-density parity check codes Aug 21, 2006 Issued
Array ( [id] => 4996247 [patent_doc_number] => 20070011592 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-11 [patent_title] => 'Decoder architecture for Reed Solomon codes' [patent_app_type] => utility [patent_app_number] => 11/505451 [patent_app_country] => US [patent_app_date] => 2006-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6441 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0011/20070011592.pdf [firstpage_image] =>[orig_patent_app_number] => 11505451 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/505451
Decoder architecture for Reed Solomon codes Aug 16, 2006 Abandoned
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