Search

Shelly A. Chase

Examiner (ID: 3566, Phone: (571)272-3816 , Office: P/2112 )

Most Active Art Unit
2112
Art Unit(s)
2784, 2786, 2133, 2112
Total Applications
2020
Issued Applications
1860
Pending Applications
102
Abandoned Applications
74

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6035687 [patent_doc_number] => 20020019963 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-14 [patent_title] => 'Tool to reconfigure pin connections between a DUT and a tester' [patent_app_type] => new [patent_app_number] => 09/816647 [patent_app_country] => US [patent_app_date] => 2001-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3024 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20020019963.pdf [firstpage_image] =>[orig_patent_app_number] => 09816647 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/816647
Tool to reconfigure pin connections between a DUT and a tester Mar 21, 2001 Issued
Array ( [id] => 1027756 [patent_doc_number] => 06886124 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-04-26 [patent_title] => 'Low hardware overhead scan based 3-weight weighted random BIST architectures' [patent_app_type] => utility [patent_app_number] => 09/805899 [patent_app_country] => US [patent_app_date] => 2001-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 20368 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/886/06886124.pdf [firstpage_image] =>[orig_patent_app_number] => 09805899 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/805899
Low hardware overhead scan based 3-weight weighted random BIST architectures Mar 14, 2001 Issued
Array ( [id] => 6889904 [patent_doc_number] => 20010025359 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-09-27 [patent_title] => 'Error detection and correction method in a computer system and main memory controller of the same' [patent_app_type] => new [patent_app_number] => 09/805169 [patent_app_country] => US [patent_app_date] => 2001-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7611 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0025/20010025359.pdf [firstpage_image] =>[orig_patent_app_number] => 09805169 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/805169
Error detection and correction method in a computer system and main memory controller of the same Mar 13, 2001 Issued
Array ( [id] => 1186738 [patent_doc_number] => 06738945 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-05-18 [patent_title] => 'Signal transmission device and method for avoiding transmission error' [patent_app_type] => B2 [patent_app_number] => 09/805621 [patent_app_country] => US [patent_app_date] => 2001-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 2974 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/738/06738945.pdf [firstpage_image] =>[orig_patent_app_number] => 09805621 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/805621
Signal transmission device and method for avoiding transmission error Mar 13, 2001 Issued
Array ( [id] => 1234541 [patent_doc_number] => 06697974 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-02-24 [patent_title] => 'Method and apparatus for adaptively compensating skews during data transmission on a bus' [patent_app_type] => B2 [patent_app_number] => 09/804799 [patent_app_country] => US [patent_app_date] => 2001-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3657 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/697/06697974.pdf [firstpage_image] =>[orig_patent_app_number] => 09804799 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/804799
Method and apparatus for adaptively compensating skews during data transmission on a bus Mar 13, 2001 Issued
Array ( [id] => 5848551 [patent_doc_number] => 20020133765 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-19 [patent_title] => 'Memory testing method and apparatus' [patent_app_type] => new [patent_app_number] => 09/804837 [patent_app_country] => US [patent_app_date] => 2001-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2841 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20020133765.pdf [firstpage_image] =>[orig_patent_app_number] => 09804837 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/804837
Memory testing method and apparatus Mar 12, 2001 Issued
Array ( [id] => 1181550 [patent_doc_number] => 06754872 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-22 [patent_title] => 'Method and apparatus for reducing channel distortion in a wireless communications network' [patent_app_type] => B2 [patent_app_number] => 09/805526 [patent_app_country] => US [patent_app_date] => 2001-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4190 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/754/06754872.pdf [firstpage_image] =>[orig_patent_app_number] => 09805526 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/805526
Method and apparatus for reducing channel distortion in a wireless communications network Mar 12, 2001 Issued
Array ( [id] => 6889907 [patent_doc_number] => 20010025362 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-09-27 [patent_title] => 'Sequential decoding apparatus and method' [patent_app_type] => new [patent_app_number] => 09/803949 [patent_app_country] => US [patent_app_date] => 2001-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 11117 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0025/20010025362.pdf [firstpage_image] =>[orig_patent_app_number] => 09803949 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/803949
Sequential decoding apparatus and method Mar 12, 2001 Issued
Array ( [id] => 6534051 [patent_doc_number] => 20020026617 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-28 [patent_title] => 'Data processing method and apparatus, recording medium, reproducidng method and apparatus using the same method' [patent_app_type] => new [patent_app_number] => 09/804242 [patent_app_country] => US [patent_app_date] => 2001-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 12082 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20020026617.pdf [firstpage_image] =>[orig_patent_app_number] => 09804242 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/804242
Data processing method and apparatus, recording medium, reproducing method and apparatus using the same method Mar 12, 2001 Issued
Array ( [id] => 6988823 [patent_doc_number] => 20010037485 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-01 [patent_title] => 'Method and apparatus for adaptively coding a data signal' [patent_app_type] => new [patent_app_number] => 09/804877 [patent_app_country] => US [patent_app_date] => 2001-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4556 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20010037485.pdf [firstpage_image] =>[orig_patent_app_number] => 09804877 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/804877
Method and apparatus for adaptively coding a data signal Mar 12, 2001 Issued
Array ( [id] => 1192677 [patent_doc_number] => 06735731 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-05-11 [patent_title] => 'Architecture for built-in self-test of parallel optical transceivers' [patent_app_type] => B2 [patent_app_number] => 09/803077 [patent_app_country] => US [patent_app_date] => 2001-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3973 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/735/06735731.pdf [firstpage_image] =>[orig_patent_app_number] => 09803077 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/803077
Architecture for built-in self-test of parallel optical transceivers Mar 8, 2001 Issued
Array ( [id] => 1181496 [patent_doc_number] => 06754862 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-22 [patent_title] => 'Gaining access to internal nodes in a PLD' [patent_app_type] => B1 [patent_app_number] => 09/802480 [patent_app_country] => US [patent_app_date] => 2001-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 7496 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/754/06754862.pdf [firstpage_image] =>[orig_patent_app_number] => 09802480 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/802480
Gaining access to internal nodes in a PLD Mar 8, 2001 Issued
Array ( [id] => 1201155 [patent_doc_number] => 06728928 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-04-27 [patent_title] => 'Modified viterbi detector for jitter noise dominant channels' [patent_app_type] => B2 [patent_app_number] => 09/681233 [patent_app_country] => US [patent_app_date] => 2001-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 5999 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/728/06728928.pdf [firstpage_image] =>[orig_patent_app_number] => 09681233 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/681233
Modified viterbi detector for jitter noise dominant channels Mar 1, 2001 Issued
Array ( [id] => 1186465 [patent_doc_number] => 06742150 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-25 [patent_title] => 'Low redesign application-specific module' [patent_app_type] => B1 [patent_app_number] => 09/806105 [patent_app_country] => US [patent_app_date] => 2001-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1351 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/742/06742150.pdf [firstpage_image] =>[orig_patent_app_number] => 09806105 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/806105
Low redesign application-specific module Feb 27, 2001 Issued
Array ( [id] => 1412769 [patent_doc_number] => 06553538 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-22 [patent_title] => 'Method and apparatus for providing error protection for over the air file transfer' [patent_app_type] => B2 [patent_app_number] => 09/784996 [patent_app_country] => US [patent_app_date] => 2001-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7459 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/553/06553538.pdf [firstpage_image] =>[orig_patent_app_number] => 09784996 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/784996
Method and apparatus for providing error protection for over the air file transfer Feb 13, 2001 Issued
Array ( [id] => 6885471 [patent_doc_number] => 20010039636 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-08 [patent_title] => 'System and method employing a modular decoder for decoding turbo and turbo-like codes in a communications network' [patent_app_type] => new [patent_app_number] => 09/781658 [patent_app_country] => US [patent_app_date] => 2001-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7937 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0039/20010039636.pdf [firstpage_image] =>[orig_patent_app_number] => 09781658 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/781658
System and method employing a modular decoder for decoding turbo and turbo-like codes in a communications network Feb 11, 2001 Issued
Array ( [id] => 6562689 [patent_doc_number] => 20020138806 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-26 [patent_title] => 'Versatile serial concatenated convolutional codes' [patent_app_type] => new [patent_app_number] => 09/781130 [patent_app_country] => US [patent_app_date] => 2001-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4521 [patent_no_of_claims] => 90 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20020138806.pdf [firstpage_image] =>[orig_patent_app_number] => 09781130 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/781130
Versatile serial concatenated convolutional codes Feb 8, 2001 Issued
Array ( [id] => 1110002 [patent_doc_number] => 06813742 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-02 [patent_title] => 'High speed turbo codes decoder for 3G using pipelined SISO log-map decoders architecture' [patent_app_type] => B2 [patent_app_number] => 09/681093 [patent_app_country] => US [patent_app_date] => 2001-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 25 [patent_no_of_words] => 4727 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/813/06813742.pdf [firstpage_image] =>[orig_patent_app_number] => 09681093 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/681093
High speed turbo codes decoder for 3G using pipelined SISO log-map decoders architecture Jan 1, 2001 Issued
Array ( [id] => 6245529 [patent_doc_number] => 20020046374 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-18 [patent_title] => 'Method of testing memory device, method of manufacturing memory device, apparatus for testing memory device, method of testing memory module, method of manufacturing memory module, apparatus for testing memory module and method of manufacturing computer' [patent_app_type] => new [patent_app_number] => 09/736282 [patent_app_country] => US [patent_app_date] => 2000-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 12999 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20020046374.pdf [firstpage_image] =>[orig_patent_app_number] => 09736282 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/736282
Method of testing memory device, method of manufacturing memory device, apparatus for testing memory device, method of testing memory module, method of manufacturing memory module, apparatus for testing memory module and method of manufacturing computer Dec 14, 2000 Abandoned
Array ( [id] => 1234595 [patent_doc_number] => 06697990 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-02-24 [patent_title] => 'Interleaver design for parsed parallel concatenated codes' [patent_app_type] => B2 [patent_app_number] => 09/734841 [patent_app_country] => US [patent_app_date] => 2000-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 7381 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/697/06697990.pdf [firstpage_image] =>[orig_patent_app_number] => 09734841 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/734841
Interleaver design for parsed parallel concatenated codes Dec 12, 2000 Issued
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