Search

Shelly A. Chase

Examiner (ID: 3566, Phone: (571)272-3816 , Office: P/2112 )

Most Active Art Unit
2112
Art Unit(s)
2784, 2786, 2133, 2112
Total Applications
2020
Issued Applications
1860
Pending Applications
102
Abandoned Applications
74

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1037239 [patent_doc_number] => 06877129 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-04-05 [patent_title] => 'Method for measuring the receiver-side bit error rate of a DVB transmission system' [patent_app_type] => utility [patent_app_number] => 09/958344 [patent_app_country] => US [patent_app_date] => 2000-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1636 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/877/06877129.pdf [firstpage_image] =>[orig_patent_app_number] => 09958344 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/958344
Method for measuring the receiver-side bit error rate of a DVB transmission system Mar 28, 2000 Issued
Array ( [id] => 4350483 [patent_doc_number] => 06321359 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'Data ordering for cache data transfer' [patent_app_type] => 1 [patent_app_number] => 9/517038 [patent_app_country] => US [patent_app_date] => 2000-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 2923 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 15 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/321/06321359.pdf [firstpage_image] =>[orig_patent_app_number] => 517038 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/517038
Data ordering for cache data transfer Mar 1, 2000 Issued
Array ( [id] => 1309262 [patent_doc_number] => 06629275 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-30 [patent_title] => 'Reinstate apparatus and method to recreate data background for testing SRAM' [patent_app_type] => B1 [patent_app_number] => 09/513662 [patent_app_country] => US [patent_app_date] => 2000-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3847 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/629/06629275.pdf [firstpage_image] =>[orig_patent_app_number] => 09513662 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/513662
Reinstate apparatus and method to recreate data background for testing SRAM Feb 24, 2000 Issued
Array ( [id] => 1311757 [patent_doc_number] => 06625762 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-23 [patent_title] => 'Interleaving device and method for turbocoding and turbodecoding' [patent_app_type] => B1 [patent_app_number] => 09/513468 [patent_app_country] => US [patent_app_date] => 2000-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 10081 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 24 [patent_words_short_claim] => 19 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/625/06625762.pdf [firstpage_image] =>[orig_patent_app_number] => 09513468 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/513468
Interleaving device and method for turbocoding and turbodecoding Feb 24, 2000 Issued
Array ( [id] => 1402096 [patent_doc_number] => 06564349 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-13 [patent_title] => 'Built-in self-test systems and methods for integrated circuit baseband quadrature modulators' [patent_app_type] => B1 [patent_app_number] => 09/512950 [patent_app_country] => US [patent_app_date] => 2000-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4849 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/564/06564349.pdf [firstpage_image] =>[orig_patent_app_number] => 09512950 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/512950
Built-in self-test systems and methods for integrated circuit baseband quadrature modulators Feb 24, 2000 Issued
Array ( [id] => 1201127 [patent_doc_number] => 06728913 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-27 [patent_title] => 'Data recycling in memory' [patent_app_type] => B1 [patent_app_number] => 09/513698 [patent_app_country] => US [patent_app_date] => 2000-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 1467 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/728/06728913.pdf [firstpage_image] =>[orig_patent_app_number] => 09513698 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/513698
Data recycling in memory Feb 24, 2000 Issued
Array ( [id] => 1125034 [patent_doc_number] => 06799290 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-09-28 [patent_title] => 'Data path calibration and testing mode using a data bus for semiconductor memories' [patent_app_type] => B1 [patent_app_number] => 09/512756 [patent_app_country] => US [patent_app_date] => 2000-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 4279 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/799/06799290.pdf [firstpage_image] =>[orig_patent_app_number] => 09512756 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/512756
Data path calibration and testing mode using a data bus for semiconductor memories Feb 24, 2000 Issued
Array ( [id] => 1412499 [patent_doc_number] => 06553521 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-22 [patent_title] => 'Method for efficient analysis semiconductor failures' [patent_app_type] => B1 [patent_app_number] => 09/511169 [patent_app_country] => US [patent_app_date] => 2000-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 3016 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/553/06553521.pdf [firstpage_image] =>[orig_patent_app_number] => 09511169 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/511169
Method for efficient analysis semiconductor failures Feb 23, 2000 Issued
Array ( [id] => 1431608 [patent_doc_number] => 06519733 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-11 [patent_title] => 'Method and apparatus for high integrity hardware memory compression' [patent_app_type] => B1 [patent_app_number] => 09/511849 [patent_app_country] => US [patent_app_date] => 2000-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3781 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/519/06519733.pdf [firstpage_image] =>[orig_patent_app_number] => 09511849 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/511849
Method and apparatus for high integrity hardware memory compression Feb 22, 2000 Issued
Array ( [id] => 1429625 [patent_doc_number] => 06530046 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-04 [patent_title] => 'Circuit, semiconductor device and method for enhancing test efficiency of function modules' [patent_app_type] => B1 [patent_app_number] => 09/511189 [patent_app_country] => US [patent_app_date] => 2000-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5136 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/530/06530046.pdf [firstpage_image] =>[orig_patent_app_number] => 09511189 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/511189
Circuit, semiconductor device and method for enhancing test efficiency of function modules Feb 22, 2000 Issued
Array ( [id] => 1311875 [patent_doc_number] => 06625779 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-23 [patent_title] => 'Transmission channel error detection code addition apparatus and error detection apparatus' [patent_app_type] => B1 [patent_app_number] => 09/510900 [patent_app_country] => US [patent_app_date] => 2000-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 1899 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/625/06625779.pdf [firstpage_image] =>[orig_patent_app_number] => 09510900 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/510900
Transmission channel error detection code addition apparatus and error detection apparatus Feb 22, 2000 Issued
Array ( [id] => 1412513 [patent_doc_number] => 06553522 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-22 [patent_title] => 'Valuation of tester accuracy' [patent_app_type] => B1 [patent_app_number] => 09/510101 [patent_app_country] => US [patent_app_date] => 2000-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 4435 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/553/06553522.pdf [firstpage_image] =>[orig_patent_app_number] => 09510101 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/510101
Valuation of tester accuracy Feb 21, 2000 Issued
Array ( [id] => 1329400 [patent_doc_number] => 06606720 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-08-12 [patent_title] => 'Scan structure for CMOS storage elements' [patent_app_type] => B1 [patent_app_number] => 09/510006 [patent_app_country] => US [patent_app_date] => 2000-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5150 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/606/06606720.pdf [firstpage_image] =>[orig_patent_app_number] => 09510006 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/510006
Scan structure for CMOS storage elements Feb 21, 2000 Issued
Array ( [id] => 7962143 [patent_doc_number] => 06681358 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-20 [patent_title] => 'Parallel testing of a multiport memory' [patent_app_type] => B1 [patent_app_number] => 09/510009 [patent_app_country] => US [patent_app_date] => 2000-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 4988 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/681/06681358.pdf [firstpage_image] =>[orig_patent_app_number] => 09510009 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/510009
Parallel testing of a multiport memory Feb 21, 2000 Issued
Array ( [id] => 1432420 [patent_doc_number] => 06505312 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-07 [patent_title] => 'Integrated circuit tester' [patent_app_type] => B1 [patent_app_number] => 09/510362 [patent_app_country] => US [patent_app_date] => 2000-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2293 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/505/06505312.pdf [firstpage_image] =>[orig_patent_app_number] => 09510362 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/510362
Integrated circuit tester Feb 21, 2000 Issued
Array ( [id] => 1430650 [patent_doc_number] => 06526535 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-25 [patent_title] => 'Synchronous data adaptor' [patent_app_type] => B1 [patent_app_number] => 09/507829 [patent_app_country] => US [patent_app_date] => 2000-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 13992 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/526/06526535.pdf [firstpage_image] =>[orig_patent_app_number] => 09507829 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/507829
Synchronous data adaptor Feb 21, 2000 Issued
Array ( [id] => 1407595 [patent_doc_number] => 06560730 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-06 [patent_title] => 'Method and apparatus for testing a non-volatile memory array having a low number of output pins' [patent_app_type] => B1 [patent_app_number] => 09/507234 [patent_app_country] => US [patent_app_date] => 2000-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1350 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/560/06560730.pdf [firstpage_image] =>[orig_patent_app_number] => 09507234 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/507234
Method and apparatus for testing a non-volatile memory array having a low number of output pins Feb 17, 2000 Issued
Array ( [id] => 1412415 [patent_doc_number] => 06553516 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-22 [patent_title] => 'Interleaving method, interleaving apparatus, turbo encoding method, and turbo encoder' [patent_app_type] => B1 [patent_app_number] => 09/506684 [patent_app_country] => US [patent_app_date] => 2000-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 6602 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 19 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/553/06553516.pdf [firstpage_image] =>[orig_patent_app_number] => 09506684 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/506684
Interleaving method, interleaving apparatus, turbo encoding method, and turbo encoder Feb 17, 2000 Issued
Array ( [id] => 1348825 [patent_doc_number] => 06598204 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-22 [patent_title] => 'System and method of turbo decoding' [patent_app_type] => B1 [patent_app_number] => 09/507545 [patent_app_country] => US [patent_app_date] => 2000-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 33 [patent_no_of_words] => 13311 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 21 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/598/06598204.pdf [firstpage_image] =>[orig_patent_app_number] => 09507545 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/507545
System and method of turbo decoding Feb 17, 2000 Issued
Array ( [id] => 1357723 [patent_doc_number] => 06591393 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-08 [patent_title] => 'Masking error detection/correction latency in multilevel cache transfers' [patent_app_type] => B1 [patent_app_number] => 09/507208 [patent_app_country] => US [patent_app_date] => 2000-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3530 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/591/06591393.pdf [firstpage_image] =>[orig_patent_app_number] => 09507208 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/507208
Masking error detection/correction latency in multilevel cache transfers Feb 17, 2000 Issued
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