Search

Shelly A. Chase

Examiner (ID: 3566, Phone: (571)272-3816 , Office: P/2112 )

Most Active Art Unit
2112
Art Unit(s)
2784, 2786, 2133, 2112
Total Applications
2020
Issued Applications
1860
Pending Applications
102
Abandoned Applications
74

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7638556 [patent_doc_number] => 06397365 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-28 [patent_title] => 'Memory error correction using redundant sliced memory and standard ECC mechanisms' [patent_app_type] => B1 [patent_app_number] => 09/313849 [patent_app_country] => US [patent_app_date] => 1999-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 3720 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 19 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/397/06397365.pdf [firstpage_image] =>[orig_patent_app_number] => 09313849 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/313849
Memory error correction using redundant sliced memory and standard ECC mechanisms May 17, 1999 Issued
Array ( [id] => 4350440 [patent_doc_number] => 06321356 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'Programmable pattern generator' [patent_app_type] => 1 [patent_app_number] => 9/314046 [patent_app_country] => US [patent_app_date] => 1999-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7933 [patent_no_of_claims] => 63 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/321/06321356.pdf [firstpage_image] =>[orig_patent_app_number] => 314046 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/314046
Programmable pattern generator May 17, 1999 Issued
Array ( [id] => 1438769 [patent_doc_number] => 06357027 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-12 [patent_title] => 'On chip data comparator with variable data and compare result compression' [patent_app_type] => B1 [patent_app_number] => 09/313016 [patent_app_country] => US [patent_app_date] => 1999-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3313 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/357/06357027.pdf [firstpage_image] =>[orig_patent_app_number] => 09313016 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/313016
On chip data comparator with variable data and compare result compression May 16, 1999 Issued
Array ( [id] => 1481361 [patent_doc_number] => 06389569 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-14 [patent_title] => 'Recording medium for storing real time recording/reproduction information, method and apparatus for recording and reproducing in real time, and file operating method using the same' [patent_app_type] => B1 [patent_app_number] => 09/304279 [patent_app_country] => US [patent_app_date] => 1999-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 26 [patent_no_of_words] => 7234 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 17 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/389/06389569.pdf [firstpage_image] =>[orig_patent_app_number] => 09304279 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/304279
Recording medium for storing real time recording/reproduction information, method and apparatus for recording and reproducing in real time, and file operating method using the same May 2, 1999 Issued
Array ( [id] => 4371816 [patent_doc_number] => 06216251 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-10 [patent_title] => 'On-chip error detection and correction system for an embedded non-volatile memory array and method of operation' [patent_app_type] => 1 [patent_app_number] => 9/302505 [patent_app_country] => US [patent_app_date] => 1999-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4942 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/216/06216251.pdf [firstpage_image] =>[orig_patent_app_number] => 302505 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/302505
On-chip error detection and correction system for an embedded non-volatile memory array and method of operation Apr 29, 1999 Issued
Array ( [id] => 1501726 [patent_doc_number] => 06405334 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-11 [patent_title] => 'Method and apparatus characterizing AC parameters of a field programmable gate array internal cell array' [patent_app_type] => B1 [patent_app_number] => 09/301358 [patent_app_country] => US [patent_app_date] => 1999-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 3972 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/405/06405334.pdf [firstpage_image] =>[orig_patent_app_number] => 09301358 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/301358
Method and apparatus characterizing AC parameters of a field programmable gate array internal cell array Apr 28, 1999 Issued
Array ( [id] => 4310989 [patent_doc_number] => 06212659 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'Method and apparatus for providing error protection for over the air file transfer' [patent_app_type] => 1 [patent_app_number] => 9/287411 [patent_app_country] => US [patent_app_date] => 1999-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7481 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/212/06212659.pdf [firstpage_image] =>[orig_patent_app_number] => 287411 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/287411
Method and apparatus for providing error protection for over the air file transfer Apr 6, 1999 Issued
Array ( [id] => 1526589 [patent_doc_number] => 06353911 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-05 [patent_title] => 'Iterative demapping' [patent_app_type] => B1 [patent_app_number] => 09/285580 [patent_app_country] => US [patent_app_date] => 1999-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2598 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 18 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/353/06353911.pdf [firstpage_image] =>[orig_patent_app_number] => 09285580 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/285580
Iterative demapping Apr 1, 1999 Issued
Array ( [id] => 1513475 [patent_doc_number] => 06442724 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-27 [patent_title] => 'Failure capture apparatus and method for automatic test equipment' [patent_app_type] => B1 [patent_app_number] => 09/285857 [patent_app_country] => US [patent_app_date] => 1999-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5109 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/442/06442724.pdf [firstpage_image] =>[orig_patent_app_number] => 09285857 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/285857
Failure capture apparatus and method for automatic test equipment Apr 1, 1999 Issued
Array ( [id] => 1540220 [patent_doc_number] => 06338155 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-08 [patent_title] => 'Data generation method and apparatus' [patent_app_type] => B1 [patent_app_number] => 09/285457 [patent_app_country] => US [patent_app_date] => 1999-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 6337 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/338/06338155.pdf [firstpage_image] =>[orig_patent_app_number] => 09285457 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/285457
Data generation method and apparatus Apr 1, 1999 Issued
Array ( [id] => 1497939 [patent_doc_number] => 06343367 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-29 [patent_title] => 'Error correction system for five or more errors' [patent_app_type] => B1 [patent_app_number] => 09/277785 [patent_app_country] => US [patent_app_date] => 1999-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 6 [patent_no_of_words] => 6238 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/343/06343367.pdf [firstpage_image] =>[orig_patent_app_number] => 09277785 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/277785
Error correction system for five or more errors Mar 28, 1999 Issued
Array ( [id] => 1431588 [patent_doc_number] => 06519724 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-11 [patent_title] => 'Communication systems, circuits, circuit systems and methods of operating a circuit' [patent_app_type] => B1 [patent_app_number] => 09/274293 [patent_app_country] => US [patent_app_date] => 1999-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 4923 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/519/06519724.pdf [firstpage_image] =>[orig_patent_app_number] => 09274293 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/274293
Communication systems, circuits, circuit systems and methods of operating a circuit Mar 21, 1999 Issued
Array ( [id] => 4325142 [patent_doc_number] => 06327682 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-04 [patent_title] => 'Wafer burn-in design for DRAM and FeRAM devices' [patent_app_type] => 1 [patent_app_number] => 9/274001 [patent_app_country] => US [patent_app_date] => 1999-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1877 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/327/06327682.pdf [firstpage_image] =>[orig_patent_app_number] => 274001 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/274001
Wafer burn-in design for DRAM and FeRAM devices Mar 21, 1999 Issued
Array ( [id] => 7634941 [patent_doc_number] => 06381725 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-30 [patent_title] => 'Disk device and data error correction method thereof' [patent_app_type] => B1 [patent_app_number] => 09/272880 [patent_app_country] => US [patent_app_date] => 1999-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6730 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/381/06381725.pdf [firstpage_image] =>[orig_patent_app_number] => 09272880 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/272880
Disk device and data error correction method thereof Mar 18, 1999 Issued
Array ( [id] => 1573869 [patent_doc_number] => 06499122 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-24 [patent_title] => 'Adjustable voltage boundary scan adapter for emulation and test' [patent_app_type] => B1 [patent_app_number] => 09/265652 [patent_app_country] => US [patent_app_date] => 1999-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 4937 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/499/06499122.pdf [firstpage_image] =>[orig_patent_app_number] => 09265652 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/265652
Adjustable voltage boundary scan adapter for emulation and test Mar 9, 1999 Issued
Array ( [id] => 4293100 [patent_doc_number] => 06247155 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-12 [patent_title] => 'Tool to reconfigure pin connections between a DUT and a tester' [patent_app_type] => 1 [patent_app_number] => 9/262761 [patent_app_country] => US [patent_app_date] => 1999-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2963 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/247/06247155.pdf [firstpage_image] =>[orig_patent_app_number] => 262761 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/262761
Tool to reconfigure pin connections between a DUT and a tester Mar 3, 1999 Issued
Array ( [id] => 4110945 [patent_doc_number] => 06134691 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-17 [patent_title] => 'NLTS correction circuit' [patent_app_type] => 1 [patent_app_number] => 9/258252 [patent_app_country] => US [patent_app_date] => 1999-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 37 [patent_no_of_words] => 10283 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/134/06134691.pdf [firstpage_image] =>[orig_patent_app_number] => 258252 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/258252
NLTS correction circuit Feb 24, 1999 Issued
Array ( [id] => 1475151 [patent_doc_number] => 06408413 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-18 [patent_title] => 'Hierarchical access of test access ports in embedded core integrated circuits' [patent_app_type] => B1 [patent_app_number] => 09/252573 [patent_app_country] => US [patent_app_date] => 1999-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 29 [patent_no_of_words] => 10936 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/408/06408413.pdf [firstpage_image] =>[orig_patent_app_number] => 09252573 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/252573
Hierarchical access of test access ports in embedded core integrated circuits Feb 17, 1999 Issued
Array ( [id] => 1497947 [patent_doc_number] => 06343368 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-29 [patent_title] => 'Method and system for fast maximum a posteriori decoding' [patent_app_type] => B1 [patent_app_number] => 09/252028 [patent_app_country] => US [patent_app_date] => 1999-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5818 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/343/06343368.pdf [firstpage_image] =>[orig_patent_app_number] => 09252028 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/252028
Method and system for fast maximum a posteriori decoding Feb 17, 1999 Issued
Array ( [id] => 1604534 [patent_doc_number] => 06434720 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'Method of checking data integrity for a RAID 1 system' [patent_app_type] => B1 [patent_app_number] => 09/251954 [patent_app_country] => US [patent_app_date] => 1999-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5986 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/434/06434720.pdf [firstpage_image] =>[orig_patent_app_number] => 09251954 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/251954
Method of checking data integrity for a RAID 1 system Feb 16, 1999 Issued
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