Shengjun Wang
Examiner (ID: 238, Phone: (571)272-0632 , Office: P/1627 )
Most Active Art Unit | 1627 |
Art Unit(s) | 1617, 1627 |
Total Applications | 2560 |
Issued Applications | 1072 |
Pending Applications | 239 |
Abandoned Applications | 1249 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 4275646
[patent_doc_number] => 06281095
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-08-28
[patent_title] => 'Process of manufacturing silicon-on-insulator chip having an isolation barrier for reliability'
[patent_app_type] => 1
[patent_app_number] => 9/148918
[patent_app_country] => US
[patent_app_date] => 1998-09-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 15
[patent_no_of_words] => 5209
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/281/06281095.pdf
[firstpage_image] =>[orig_patent_app_number] => 148918
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/148918 | Process of manufacturing silicon-on-insulator chip having an isolation barrier for reliability | Sep 3, 1998 | Issued |
Array
(
[id] => 4350032
[patent_doc_number] => 06291276
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-09-18
[patent_title] => 'Cross coupled thin film transistors and static random access memory cell'
[patent_app_type] => 1
[patent_app_number] => 9/136902
[patent_app_country] => US
[patent_app_date] => 1998-08-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[patent_no_of_words] => 3689
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/291/06291276.pdf
[firstpage_image] =>[orig_patent_app_number] => 136902
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/136902 | Cross coupled thin film transistors and static random access memory cell | Aug 18, 1998 | Issued |
Array
(
[id] => 4169342
[patent_doc_number] => 06140204
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-10-31
[patent_title] => 'Process for producing a semiconductor device having hemispherical grains (HSG)'
[patent_app_type] => 1
[patent_app_number] => 9/118931
[patent_app_country] => US
[patent_app_date] => 1998-07-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 4590
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/140/06140204.pdf
[firstpage_image] =>[orig_patent_app_number] => 118931
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/118931 | Process for producing a semiconductor device having hemispherical grains (HSG) | Jul 19, 1998 | Issued |
Array
(
[id] => 4131070
[patent_doc_number] => 06146951
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-11-14
[patent_title] => 'Method of manufacturing semiconductor device for preventing electrostatic discharge'
[patent_app_type] => 1
[patent_app_number] => 9/103751
[patent_app_country] => US
[patent_app_date] => 1998-06-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 3830
[patent_no_of_claims] => 10
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[patent_words_short_claim] => 170
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/146/06146951.pdf
[firstpage_image] =>[orig_patent_app_number] => 103751
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/103751 | Method of manufacturing semiconductor device for preventing electrostatic discharge | Jun 23, 1998 | Issued |
Array
(
[id] => 4235108
[patent_doc_number] => 06143583
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-11-07
[patent_title] => 'Dissolved wafer fabrication process and associated microelectromechanical device having a support substrate with spacing mesas'
[patent_app_type] => 1
[patent_app_number] => 9/093492
[patent_app_country] => US
[patent_app_date] => 1998-06-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 23
[patent_no_of_words] => 6683
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/143/06143583.pdf
[firstpage_image] =>[orig_patent_app_number] => 093492
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/093492 | Dissolved wafer fabrication process and associated microelectromechanical device having a support substrate with spacing mesas | Jun 7, 1998 | Issued |
Array
(
[id] => 4286576
[patent_doc_number] => 06268244
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-07-31
[patent_title] => 'Method of fabricating capacitors of a memory cell array'
[patent_app_type] => 1
[patent_app_number] => 9/090902
[patent_app_country] => US
[patent_app_date] => 1998-06-05
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[patent_no_of_words] => 4573
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[pdf_file] => patents/06/268/06268244.pdf
[firstpage_image] =>[orig_patent_app_number] => 090902
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/090902 | Method of fabricating capacitors of a memory cell array | Jun 4, 1998 | Issued |
Array
(
[id] => 4191913
[patent_doc_number] => 06130172
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-10-10
[patent_title] => 'Radiation hardened dielectric for EEPROM'
[patent_app_type] => 1
[patent_app_number] => 9/061602
[patent_app_country] => US
[patent_app_date] => 1998-04-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 20
[patent_no_of_words] => 4319
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[patent_words_short_claim] => 93
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[pdf_file] => patents/06/130/06130172.pdf
[firstpage_image] =>[orig_patent_app_number] => 061602
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/061602 | Radiation hardened dielectric for EEPROM | Apr 15, 1998 | Issued |
Array
(
[id] => 4156152
[patent_doc_number] => 06156638
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-12-05
[patent_title] => 'Integrated circuitry and method of restricting diffusion from one material to another'
[patent_app_type] => 1
[patent_app_number] => 9/058612
[patent_app_country] => US
[patent_app_date] => 1998-04-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 1690
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 178
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/156/06156638.pdf
[firstpage_image] =>[orig_patent_app_number] => 058612
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/058612 | Integrated circuitry and method of restricting diffusion from one material to another | Apr 9, 1998 | Issued |
Array
(
[id] => 4154784
[patent_doc_number] => 06103615
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-15
[patent_title] => 'Corrosion sensitivity structures for vias and contact holes in integrated circuits'
[patent_app_type] => 1
[patent_app_number] => 9/045062
[patent_app_country] => US
[patent_app_date] => 1998-03-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 7270
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/103/06103615.pdf
[firstpage_image] =>[orig_patent_app_number] => 045062
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/045062 | Corrosion sensitivity structures for vias and contact holes in integrated circuits | Mar 18, 1998 | Issued |
Array
(
[id] => 4155373
[patent_doc_number] => 06114221
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-09-05
[patent_title] => 'Method and apparatus for interconnecting multiple circuit chips'
[patent_app_type] => 1
[patent_app_number] => 9/039962
[patent_app_country] => US
[patent_app_date] => 1998-03-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 1733
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/114/06114221.pdf
[firstpage_image] =>[orig_patent_app_number] => 039962
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/039962 | Method and apparatus for interconnecting multiple circuit chips | Mar 15, 1998 | Issued |
Array
(
[id] => 4245421
[patent_doc_number] => 06136624
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-10-24
[patent_title] => 'Array substrate, liquid crystal display device and their manufacturing method'
[patent_app_type] => 1
[patent_app_number] => 9/038501
[patent_app_country] => US
[patent_app_date] => 1998-03-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
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[patent_no_of_words] => 8251
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/136/06136624.pdf
[firstpage_image] =>[orig_patent_app_number] => 038501
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/038501 | Array substrate, liquid crystal display device and their manufacturing method | Mar 8, 1998 | Issued |
Array
(
[id] => 4404907
[patent_doc_number] => 06271102
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-08-07
[patent_title] => 'Method and system for dicing wafers, and semiconductor structures incorporating the products thereof'
[patent_app_type] => 1
[patent_app_number] => 9/032151
[patent_app_country] => US
[patent_app_date] => 1998-02-27
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[pdf_file] => patents/06/271/06271102.pdf
[firstpage_image] =>[orig_patent_app_number] => 032151
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/032151 | Method and system for dicing wafers, and semiconductor structures incorporating the products thereof | Feb 26, 1998 | Issued |
Array
(
[id] => 4085049
[patent_doc_number] => 06025260
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-02-15
[patent_title] => 'Method for fabricating air gap with borderless contact'
[patent_app_type] => 1
[patent_app_number] => 9/019491
[patent_app_country] => US
[patent_app_date] => 1998-02-05
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[pdf_file] => patents/06/025/06025260.pdf
[firstpage_image] =>[orig_patent_app_number] => 019491
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/019491 | Method for fabricating air gap with borderless contact | Feb 4, 1998 | Issued |
Array
(
[id] => 4178192
[patent_doc_number] => 06037251
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-03-14
[patent_title] => 'Process for intermetal SOG/SOP dielectric planarization'
[patent_app_type] => 1
[patent_app_number] => 9/003153
[patent_app_country] => US
[patent_app_date] => 1998-01-06
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[pdf_file] => patents/06/037/06037251.pdf
[firstpage_image] =>[orig_patent_app_number] => 003153
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/003153 | Process for intermetal SOG/SOP dielectric planarization | Jan 5, 1998 | Issued |
Array
(
[id] => 4236814
[patent_doc_number] => 06090652
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-07-18
[patent_title] => 'Method of manufacturing a semiconductor device including implanting threshold voltage adjustment ions'
[patent_app_type] => 1
[patent_app_number] => 8/996011
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[patent_app_date] => 1997-12-22
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[pdf_file] => patents/06/090/06090652.pdf
[firstpage_image] =>[orig_patent_app_number] => 996011
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/996011 | Method of manufacturing a semiconductor device including implanting threshold voltage adjustment ions | Dec 21, 1997 | Issued |
Array
(
[id] => 4081187
[patent_doc_number] => 06054380
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-04-25
[patent_title] => 'Method and apparatus for integrating low dielectric constant materials into a multilevel metallization and interconnect structure'
[patent_app_type] => 1
[patent_app_number] => 8/987219
[patent_app_country] => US
[patent_app_date] => 1997-12-09
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[pdf_file] => patents/06/054/06054380.pdf
[firstpage_image] =>[orig_patent_app_number] => 987219
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/987219 | Method and apparatus for integrating low dielectric constant materials into a multilevel metallization and interconnect structure | Dec 8, 1997 | Issued |
Array
(
[id] => 4095085
[patent_doc_number] => 06096635
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-01
[patent_title] => 'Method for creating via hole in chip'
[patent_app_type] => 1
[patent_app_number] => 8/984299
[patent_app_country] => US
[patent_app_date] => 1997-12-03
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/096/06096635.pdf
[firstpage_image] =>[orig_patent_app_number] => 984299
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/984299 | Method for creating via hole in chip | Dec 2, 1997 | Issued |
Array
(
[id] => 1462576
[patent_doc_number] => 06350672
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-02-26
[patent_title] => 'Interconnect structure with gas dielectric compatible with unlanded vias'
[patent_app_type] => B1
[patent_app_number] => 08/948368
[patent_app_country] => US
[patent_app_date] => 1997-10-09
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[pdf_file] => patents/06/350/06350672.pdf
[firstpage_image] =>[orig_patent_app_number] => 08948368
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/948368 | Interconnect structure with gas dielectric compatible with unlanded vias | Oct 8, 1997 | Issued |