Shengjun Wang

Array ( [id] => 16065169 [patent_doc_number] => 10691534 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-23 [patent_title] => Data encoding method, data decoding method and storage controller [patent_app_type] => utility [patent_app_number] => 15/950184 [patent_app_country] => US [patent_app_date] => 2018-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 8723 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 335 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15950184 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16417645 [patent_doc_number] => 10825545 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-03 [patent_title] => Memory device loopback systems and methods [patent_app_type] => utility [patent_app_number] => 15/944455 [patent_app_country] => US [patent_app_date] => 2018-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 7787 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15944455 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16250164 [patent_doc_number] => 10749547 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-18 [patent_title] => Error detector and/or corrector checker method and apparatus [patent_app_type] => utility [patent_app_number] => 15/938505 [patent_app_country] => US [patent_app_date] => 2018-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5207 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15938505 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13906311 [patent_doc_number] => 20190042360 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-07 [patent_title] => ERROR CORRECTION CIRCUIT AND MEMORY SYSTEM INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 15/936684 [patent_app_country] => US [patent_app_date] => 2018-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3291 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15936684 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15638687 [patent_doc_number] => 10592337 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-03-17 [patent_title] => Systems and methods for distributing information across distributed storage devices [patent_app_type] => utility [patent_app_number] => 15/937754 [patent_app_country] => US [patent_app_date] => 2018-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5612 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15937754 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16200696 [patent_doc_number] => 10725859 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-28 [patent_title] => Parity generation offload using peer-to-peer data transfers in data storage system [patent_app_type] => utility [patent_app_number] => 15/936325 [patent_app_country] => US [patent_app_date] => 2018-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 18099 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 378 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15936325 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13453451 [patent_doc_number] => 20180278268 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-27 [patent_title] => METHOD FOR GENERATING A SEQUENCE FOR A POLA CODE AND MEDIUM THEREFOR AND METHOD AND APPARATUS FOR TRANSMITTING DATA USING THEREOF [patent_app_type] => utility [patent_app_number] => 15/934575 [patent_app_country] => US [patent_app_date] => 2018-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26624 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15934575 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16047703 [patent_doc_number] => 10685730 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-06-16 [patent_title] => Circuit including efficient clocking for testing memory interface [patent_app_type] => utility [patent_app_number] => 15/926414 [patent_app_country] => US [patent_app_date] => 2018-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 7482 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15926414 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13998123 [patent_doc_number] => 20190068219 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => BIT-FLIPPING DECODER FOR G-LDPC CODES WITH SYNDROME-DECODING FOR COMPONENT CODES [patent_app_type] => utility [patent_app_number] => 15/917222 [patent_app_country] => US [patent_app_date] => 2018-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9271 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15917222 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12891367 [patent_doc_number] => 20180188964 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-05 [patent_title] => MANAGED STORAGE UNIT SHUTDOWN IN A DISTRIBUTED STORAGE NETWORK [patent_app_type] => utility [patent_app_number] => 15/900525 [patent_app_country] => US [patent_app_date] => 2018-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10738 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15900525 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13843775 [patent_doc_number] => 20190025372 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-24 [patent_title] => ERROR RATE METER INCLUDED IN A SEMICONDUCTOR DIE [patent_app_type] => utility [patent_app_number] => 15/895784 [patent_app_country] => US [patent_app_date] => 2018-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7142 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15895784 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14718293 [patent_doc_number] => 20190250210 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-15 [patent_title] => System Architecture Method and Apparatus for Adaptive Hardware Fault Detection with Hardware Metrics Subsystem [patent_app_type] => utility [patent_app_number] => 15/893485 [patent_app_country] => US [patent_app_date] => 2018-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6991 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15893485 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15317261 [patent_doc_number] => 10523352 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-31 [patent_title] => Forward error correction for incomplete blocks [patent_app_type] => utility [patent_app_number] => 15/890219 [patent_app_country] => US [patent_app_date] => 2018-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 14161 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15890219 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15820301 [patent_doc_number] => 10635327 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-28 [patent_title] => Data availability during memory inaccessibility [patent_app_type] => utility [patent_app_number] => 15/885770 [patent_app_country] => US [patent_app_date] => 2018-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 14130 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15885770 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12800101 [patent_doc_number] => 20180158536 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-07 [patent_title] => Periodically Updating a Log Likelihood Ratio (LLR) Table in a Flash Memory Controller [patent_app_type] => utility [patent_app_number] => 15/884133 [patent_app_country] => US [patent_app_date] => 2018-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11058 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15884133 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14796761 [patent_doc_number] => 10401379 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-03 [patent_title] => Sensor device provided with a circuit for detection of single or multiple events for generating corresponding interrupt signals [patent_app_type] => utility [patent_app_number] => 15/884019 [patent_app_country] => US [patent_app_date] => 2018-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 5340 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15884019 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12778162 [patent_doc_number] => 20180151222 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-31 [patent_title] => SOFT INFORMATION MODULE [patent_app_type] => utility [patent_app_number] => 15/882937 [patent_app_country] => US [patent_app_date] => 2018-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9139 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15882937 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13740165 [patent_doc_number] => 20180374552 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-27 [patent_title] => MEMORY SYSTEM AND OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/881243 [patent_app_country] => US [patent_app_date] => 2018-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12034 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15881243 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15820703 [patent_doc_number] => 10635531 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-28 [patent_title] => Semiconductor memory device error correction circuit, semiconductor memory device including the same, and memory system including the same [patent_app_type] => utility [patent_app_number] => 15/870220 [patent_app_country] => US [patent_app_date] => 2018-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 28 [patent_no_of_words] => 9490 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15870220 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15047095 [patent_doc_number] => 20190334552 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-31 [patent_title] => ENCODING METHOD AND ENCODER [patent_app_type] => utility [patent_app_number] => 16/476051 [patent_app_country] => US [patent_app_date] => 2018-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12378 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16476051 [rel_patent_id] =>[rel_patent_doc_number] =>)