Search

Shengjun Wang

Examiner (ID: 18947, Phone: (571)272-0632 , Office: P/1627 )

Most Active Art Unit
1627
Art Unit(s)
1627, 1617
Total Applications
2559
Issued Applications
1079
Pending Applications
238
Abandoned Applications
1248

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11403091 [patent_doc_number] => 20170023629 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-26 [patent_title] => 'TUNING A TESTING APPARATUS FOR MEASURING SKEW' [patent_app_type] => utility [patent_app_number] => 14/803685 [patent_app_country] => US [patent_app_date] => 2015-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6859 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14803685 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/803685
Tuning a testing apparatus for measuring skew Jul 19, 2015 Issued
Array ( [id] => 11403108 [patent_doc_number] => 20170023646 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-26 [patent_title] => 'TUNING A TESTING APPARATUS FOR MEASURING SKEW' [patent_app_type] => utility [patent_app_number] => 14/803326 [patent_app_country] => US [patent_app_date] => 2015-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6831 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14803326 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/803326
Tuning a testing apparatus for measuring skew Jul 19, 2015 Issued
Array ( [id] => 11397777 [patent_doc_number] => 20170018313 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-19 [patent_title] => 'BUILT-IN SELF-TEST (BIST) ENGINE' [patent_app_type] => utility [patent_app_number] => 14/800067 [patent_app_country] => US [patent_app_date] => 2015-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3230 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14800067 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/800067
Built-in-self-test (BIST) engine configured to store a per pattern based fail status in a pattern mask register Jul 14, 2015 Issued
Array ( [id] => 11911000 [patent_doc_number] => 09779818 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-03 [patent_title] => 'Adaptation of high-order read thresholds' [patent_app_type] => utility [patent_app_number] => 14/794862 [patent_app_country] => US [patent_app_date] => 2015-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 5827 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14794862 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/794862
Adaptation of high-order read thresholds Jul 8, 2015 Issued
Array ( [id] => 11313211 [patent_doc_number] => 20160349320 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-01 [patent_title] => 'REMOTE BUS WRAPPER FOR TESTING REMOTE CORES USING AUTOMATIC TEST PATTERN GENERATION AND OTHER TECHNIQUES' [patent_app_type] => utility [patent_app_number] => 14/794774 [patent_app_country] => US [patent_app_date] => 2015-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 17759 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14794774 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/794774
REMOTE BUS WRAPPER FOR TESTING REMOTE CORES USING AUTOMATIC TEST PATTERN GENERATION AND OTHER TECHNIQUES Jul 7, 2015 Abandoned
Array ( [id] => 11123471 [patent_doc_number] => 20160320445 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-03 [patent_title] => 'PROBELESS PARALLEL TEST SYSTEM AND METHOD FOR INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 14/792626 [patent_app_country] => US [patent_app_date] => 2015-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2793 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14792626 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/792626
PROBELESS PARALLEL TEST SYSTEM AND METHOD FOR INTEGRATED CIRCUIT Jul 6, 2015 Abandoned
Array ( [id] => 11358474 [patent_doc_number] => 09535121 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-01-03 [patent_title] => 'Methods and apparatuses to enhance timing delay fault coverage with test logic that includes partitions and scan flip-flops' [patent_app_type] => utility [patent_app_number] => 14/792429 [patent_app_country] => US [patent_app_date] => 2015-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 10810 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14792429 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/792429
Methods and apparatuses to enhance timing delay fault coverage with test logic that includes partitions and scan flip-flops Jul 5, 2015 Issued
Array ( [id] => 11344640 [patent_doc_number] => 09529044 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-12-27 [patent_title] => 'Apparatuses and methods to enhance timing delay fault coverage' [patent_app_type] => utility [patent_app_number] => 14/792426 [patent_app_country] => US [patent_app_date] => 2015-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 10751 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14792426 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/792426
Apparatuses and methods to enhance timing delay fault coverage Jul 5, 2015 Issued
Array ( [id] => 11298980 [patent_doc_number] => 09506984 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-11-29 [patent_title] => 'Protocol based automated tester stimulus generator' [patent_app_type] => utility [patent_app_number] => 14/790764 [patent_app_country] => US [patent_app_date] => 2015-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4869 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14790764 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/790764
Protocol based automated tester stimulus generator Jul 1, 2015 Issued
Array ( [id] => 11806483 [patent_doc_number] => 09547551 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-17 [patent_title] => 'Memory system having an encoding processing circuit for redundant encoding process' [patent_app_type] => utility [patent_app_number] => 14/789090 [patent_app_country] => US [patent_app_date] => 2015-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 29 [patent_no_of_words] => 8110 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14789090 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/789090
Memory system having an encoding processing circuit for redundant encoding process Jun 30, 2015 Issued
Array ( [id] => 12038841 [patent_doc_number] => 09817069 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-11-14 [patent_title] => 'Method and system for construction of a highly efficient and predictable sequential test decompression logic' [patent_app_type] => utility [patent_app_number] => 14/754403 [patent_app_country] => US [patent_app_date] => 2015-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 4275 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14754403 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/754403
Method and system for construction of a highly efficient and predictable sequential test decompression logic Jun 28, 2015 Issued
Array ( [id] => 12038838 [patent_doc_number] => 09817068 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-11-14 [patent_title] => 'Method and system for improving efficiency of sequential test compression using overscan' [patent_app_type] => utility [patent_app_number] => 14/754386 [patent_app_country] => US [patent_app_date] => 2015-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 3565 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14754386 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/754386
Method and system for improving efficiency of sequential test compression using overscan Jun 28, 2015 Issued
Array ( [id] => 11522786 [patent_doc_number] => 09606179 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-03-28 [patent_title] => 'Method and system for improving efficiency of XOR-based test compression using an embedded serializer-deserializer' [patent_app_type] => utility [patent_app_number] => 14/754351 [patent_app_country] => US [patent_app_date] => 2015-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2991 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14754351 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/754351
Method and system for improving efficiency of XOR-based test compression using an embedded serializer-deserializer Jun 28, 2015 Issued
Array ( [id] => 13677885 [patent_doc_number] => 20160377676 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-29 [patent_title] => INTEGRATED CIRCUIT INCLUDING OVERLAPPING SCAN DOMAINS [patent_app_type] => utility [patent_app_number] => 14/747924 [patent_app_country] => US [patent_app_date] => 2015-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3798 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14747924 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/747924
INTEGRATED CIRCUIT INCLUDING OVERLAPPING SCAN DOMAINS Jun 22, 2015 Abandoned
Array ( [id] => 11623931 [patent_doc_number] => 20170134120 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-11 [patent_title] => 'CYCLE SLIP RESILIENT CODED MODULATION FOR FIBER-OPTIC COMMUNICATIONS' [patent_app_type] => utility [patent_app_number] => 15/318603 [patent_app_country] => US [patent_app_date] => 2015-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8544 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15318603 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/318603
Cycle slip resilient coded modulation for fiber-optic communications Jun 21, 2015 Issued
Array ( [id] => 11026656 [patent_doc_number] => 20160223612 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-04 [patent_title] => 'IEEE 1149.1 STANDARD BASED TESTING METHODS USED IN PACKAGING' [patent_app_type] => utility [patent_app_number] => 14/744790 [patent_app_country] => US [patent_app_date] => 2015-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3429 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14744790 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/744790
IEEE 1149.1 STANDARD BASED TESTING METHODS USED IN PACKAGING Jun 18, 2015 Abandoned
Array ( [id] => 11351687 [patent_doc_number] => 20160370427 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-22 [patent_title] => 'CONFIGURATION ERROR DETECTOR' [patent_app_type] => utility [patent_app_number] => 14/740825 [patent_app_country] => US [patent_app_date] => 2015-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4758 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14740825 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/740825
CONFIGURATION ERROR DETECTOR Jun 15, 2015 Abandoned
Array ( [id] => 11919132 [patent_doc_number] => 09787330 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-10 [patent_title] => 'Controller having error correction function in accordance with operating state of monitoring target' [patent_app_type] => utility [patent_app_number] => 14/733985 [patent_app_country] => US [patent_app_date] => 2015-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4949 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 306 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14733985 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/733985
Controller having error correction function in accordance with operating state of monitoring target Jun 8, 2015 Issued
Array ( [id] => 11846458 [patent_doc_number] => 09734012 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-15 [patent_title] => 'Data encoding in solid-state storage devices' [patent_app_type] => utility [patent_app_number] => 14/730321 [patent_app_country] => US [patent_app_date] => 2015-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 9590 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14730321 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/730321
Data encoding in solid-state storage devices Jun 3, 2015 Issued
Array ( [id] => 11314068 [patent_doc_number] => 20160350178 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-01 [patent_title] => 'METHODS AND SYSTEMS FOR DETECTING AND CORRECTING ERRORS IN NONVOLATILE MEMORY' [patent_app_type] => utility [patent_app_number] => 14/724899 [patent_app_country] => US [patent_app_date] => 2015-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 11555 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14724899 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/724899
Methods and systems for detecting and correcting errors in nonvolatile memory May 28, 2015 Issued
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