Shengjun Wang

Array ( [id] => 10448761 [patent_doc_number] => 20150333775 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-19 [patent_title] => 'Frozen-Bit Selection for a Polar Code Decoder' [patent_app_type] => utility [patent_app_number] => 14/482772 [patent_app_country] => US [patent_app_date] => 2014-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6874 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14482772 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11007849 [patent_doc_number] => 20160204801 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-14 [patent_title] => 'DATA PROCESSING DEVICE AND DATA PROCESSING METHOD' [patent_app_type] => utility [patent_app_number] => 14/913901 [patent_app_country] => US [patent_app_date] => 2014-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 56 [patent_figures_cnt] => 56 [patent_no_of_words] => 37570 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14913901 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10454168 [patent_doc_number] => 20150339183 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-26 [patent_title] => 'CONTROLLER, STORAGE DEVICE, AND CONTROL METHOD' [patent_app_type] => utility [patent_app_number] => 14/477432 [patent_app_country] => US [patent_app_date] => 2014-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7959 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14477432 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11803056 [patent_doc_number] => 09543983 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-10 [patent_title] => 'Decoding method, memory storage device and memory control circuit unit' [patent_app_type] => utility [patent_app_number] => 14/475585 [patent_app_country] => US [patent_app_date] => 2014-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 10506 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14475585 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10717955 [patent_doc_number] => 20160064102 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-03 [patent_title] => 'FAST AUTO SHIFT OF FAILING MEMORY DIAGNOSTICS DATA USING PATTERN DETECTION' [patent_app_type] => utility [patent_app_number] => 14/468999 [patent_app_country] => US [patent_app_date] => 2014-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4012 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14468999 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11702519 [patent_doc_number] => 09692456 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-06-27 [patent_title] => 'Product coded modulation scheme based on E8 lattice and binary and nonbinary codes' [patent_app_type] => utility [patent_app_number] => 14/466372 [patent_app_country] => US [patent_app_date] => 2014-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10028 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14466372 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10221689 [patent_doc_number] => 20150106682 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-16 [patent_title] => 'CUMULATIVE ERROR DETECTION IN DATA TRANSMISSION' [patent_app_type] => utility [patent_app_number] => 14/462205 [patent_app_country] => US [patent_app_date] => 2014-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8084 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14462205 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11238437 [patent_doc_number] => 09465073 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-10-11 [patent_title] => 'Integrated circuit (IC) for reconstructing values of flip-flops connected in a scan-chain by using a joint test action group (JTAG) interface, a method of operating the IC, and devices having the IC' [patent_app_type] => utility [patent_app_number] => 14/456341 [patent_app_country] => US [patent_app_date] => 2014-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9914 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14456341 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10236179 [patent_doc_number] => 20150121174 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-30 [patent_title] => 'SEMICONDUCTOR STORING DEVICE AND REDUNDANCY METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/453606 [patent_app_country] => US [patent_app_date] => 2014-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6269 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14453606 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10369126 [patent_doc_number] => 20150254131 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-10 [patent_title] => 'MEMORY CONTROLLER, STORAGE DEVICE AND MEMORY CONTROL METHOD' [patent_app_type] => utility [patent_app_number] => 14/445198 [patent_app_country] => US [patent_app_date] => 2014-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7202 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14445198 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11200912 [patent_doc_number] => 09431130 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-30 [patent_title] => 'Memory controller, storage device, and memory control method' [patent_app_type] => utility [patent_app_number] => 14/337372 [patent_app_country] => US [patent_app_date] => 2014-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6468 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14337372 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11181384 [patent_doc_number] => 09413390 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-08-09 [patent_title] => 'High throughput low-density parity-check (LDPC) decoder via rescheduling' [patent_app_type] => utility [patent_app_number] => 14/333436 [patent_app_country] => US [patent_app_date] => 2014-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 5541 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14333436 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11104527 [patent_doc_number] => 20160301497 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-13 [patent_title] => 'TRANSMISSION APPARATUS, CONTROL METHOD, AND PROGRAM' [patent_app_type] => utility [patent_app_number] => 15/036887 [patent_app_country] => US [patent_app_date] => 2014-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9573 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15036887 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10314264 [patent_doc_number] => 20150199267 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-16 [patent_title] => 'MEMORY CONTROLLER, SYSTEM COMPRISING MEMORY CONTROLLER, AND RELATED METHODS OF OPERATION' [patent_app_type] => utility [patent_app_number] => 14/323294 [patent_app_country] => US [patent_app_date] => 2014-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 10449 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14323294 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11807055 [patent_doc_number] => 09548137 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-17 [patent_title] => 'Integrated circuit defect detection and repair' [patent_app_type] => utility [patent_app_number] => 14/320164 [patent_app_country] => US [patent_app_date] => 2014-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 45 [patent_no_of_words] => 39858 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14320164 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10492938 [patent_doc_number] => 20150377960 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-31 [patent_title] => 'SIMULTANEOUS TRANSITION TESTING OF DIFFERENT CLOCK DOMAINS IN A DIGITAL INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 14/316468 [patent_app_country] => US [patent_app_date] => 2014-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7476 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14316468 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10485653 [patent_doc_number] => 20150370672 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-24 [patent_title] => 'TRIGGER DETECTION FOR POST CONFIGURATION TESTING OF PROGRAMMABLE LOGIC DEVICES' [patent_app_type] => utility [patent_app_number] => 14/313443 [patent_app_country] => US [patent_app_date] => 2014-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4449 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14313443 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11278639 [patent_doc_number] => 09495118 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-15 [patent_title] => 'Storing data in a directory-less dispersed storage network' [patent_app_type] => utility [patent_app_number] => 14/307625 [patent_app_country] => US [patent_app_date] => 2014-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 62 [patent_figures_cnt] => 69 [patent_no_of_words] => 41488 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14307625 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9746046 [patent_doc_number] => 20140281765 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'MEMORY CARD' [patent_app_type] => utility [patent_app_number] => 14/289078 [patent_app_country] => US [patent_app_date] => 2014-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6529 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14289078 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10956358 [patent_doc_number] => 20140359380 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-04 [patent_title] => 'RUNTIME DYNAMIC PERFORMANCE SKEW ELIMINATION' [patent_app_type] => utility [patent_app_number] => 14/266455 [patent_app_country] => US [patent_app_date] => 2014-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8206 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14266455 [rel_patent_id] =>[rel_patent_doc_number] =>)