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Shengjun Wang

Examiner (ID: 18947, Phone: (571)272-0632 , Office: P/1627 )

Most Active Art Unit
1627
Art Unit(s)
1627, 1617
Total Applications
2559
Issued Applications
1079
Pending Applications
238
Abandoned Applications
1248

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8254965 [patent_doc_number] => 20120159289 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-21 [patent_title] => 'DATA SIGNATURES TO DETERMINE SUCESSFUL COMPLETION OF MEMORY BACKUP' [patent_app_type] => utility [patent_app_number] => 13/104624 [patent_app_country] => US [patent_app_date] => 2011-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8560 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0159/20120159289.pdf [firstpage_image] =>[orig_patent_app_number] => 13104624 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/104624
Data signatures to determine successful completion of memory backup May 9, 2011 Issued
Array ( [id] => 8485170 [patent_doc_number] => 20120284576 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-08 [patent_title] => 'HARDWARE STIMULUS ENGINE FOR MEMORY RECEIVE AND TRANSMIT SIGNALS' [patent_app_type] => utility [patent_app_number] => 13/102975 [patent_app_country] => US [patent_app_date] => 2011-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6070 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13102975 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/102975
HARDWARE STIMULUS ENGINE FOR MEMORY RECEIVE AND TRANSMIT SIGNALS May 5, 2011 Abandoned
Array ( [id] => 8479261 [patent_doc_number] => 20120278668 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-01 [patent_title] => 'RUNTIME DYNAMIC PERFORMANCE SKEW ELIMINATION' [patent_app_type] => utility [patent_app_number] => 13/098143 [patent_app_country] => US [patent_app_date] => 2011-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8157 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13098143 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/098143
Runtime dynamic performance skew elimination Apr 28, 2011 Issued
Array ( [id] => 8087643 [patent_doc_number] => 08151153 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-04-03 [patent_title] => 'Scan architecture for full custom blocks' [patent_app_type] => utility [patent_app_number] => 13/093114 [patent_app_country] => US [patent_app_date] => 2011-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 14739 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/151/08151153.pdf [firstpage_image] =>[orig_patent_app_number] => 13093114 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/093114
Scan architecture for full custom blocks Apr 24, 2011 Issued
Array ( [id] => 6191221 [patent_doc_number] => 20110173505 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-14 [patent_title] => 'METHOD FOR DETECTING MEMORY ERROR' [patent_app_type] => utility [patent_app_number] => 13/053763 [patent_app_country] => US [patent_app_date] => 2011-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3709 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0173/20110173505.pdf [firstpage_image] =>[orig_patent_app_number] => 13053763 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/053763
METHOD FOR DETECTING MEMORY ERROR Mar 21, 2011 Abandoned
Array ( [id] => 8404598 [patent_doc_number] => 20120236660 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-20 [patent_title] => 'TEST SYSTEM AND TEST METHOD FOR MEMORY' [patent_app_type] => utility [patent_app_number] => 13/049036 [patent_app_country] => US [patent_app_date] => 2011-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2622 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13049036 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/049036
TEST SYSTEM AND TEST METHOD FOR MEMORY Mar 15, 2011 Abandoned
Array ( [id] => 6166726 [patent_doc_number] => 20110161750 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-30 [patent_title] => 'Pre-Code Device, and Pre-Code System and Pre-Coding Method Thereof' [patent_app_type] => utility [patent_app_number] => 13/042910 [patent_app_country] => US [patent_app_date] => 2011-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2937 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0161/20110161750.pdf [firstpage_image] =>[orig_patent_app_number] => 13042910 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/042910
Pre-code device, and pre-code system and pre-coding method thereof Mar 7, 2011 Issued
Array ( [id] => 6166692 [patent_doc_number] => 20110161735 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-30 [patent_title] => 'SEMICONDUCTOR DEVICE CONTROLLING DEBUG OPERATION OF PROCESSING UNIT IN RESPONSE TO PERMISSION OR PROHIBITION FROM OTHER PROCESSING UNIT' [patent_app_type] => utility [patent_app_number] => 13/064090 [patent_app_country] => US [patent_app_date] => 2011-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6539 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0161/20110161735.pdf [firstpage_image] =>[orig_patent_app_number] => 13064090 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/064090
Semiconductor device controlling debug operation of processing unit in response to permission or prohibition from other processing unit Mar 3, 2011 Issued
Array ( [id] => 9416912 [patent_doc_number] => 08700964 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-15 [patent_title] => 'Test apparatus and synchronization method' [patent_app_type] => utility [patent_app_number] => 13/029065 [patent_app_country] => US [patent_app_date] => 2011-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3716 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13029065 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/029065
Test apparatus and synchronization method Feb 15, 2011 Issued
Array ( [id] => 6189415 [patent_doc_number] => 20110126065 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-26 [patent_title] => 'MICROPROCESSOR COMPRISING SIGNATURE MEANS FOR DETECTING AN ATTACK BY ERROR INJECTION' [patent_app_type] => utility [patent_app_number] => 13/019143 [patent_app_country] => US [patent_app_date] => 2011-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8337 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0126/20110126065.pdf [firstpage_image] =>[orig_patent_app_number] => 13019143 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/019143
Microprocessor comprising signature means for detecting an attack by error injection Jan 31, 2011 Issued
Array ( [id] => 7537701 [patent_doc_number] => 08051344 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-01 [patent_title] => 'Semiconductor memory testing device and method of testing semiconductor using the same' [patent_app_type] => utility [patent_app_number] => 13/016074 [patent_app_country] => US [patent_app_date] => 2011-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6374 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/051/08051344.pdf [firstpage_image] =>[orig_patent_app_number] => 13016074 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/016074
Semiconductor memory testing device and method of testing semiconductor using the same Jan 27, 2011 Issued
Array ( [id] => 6088214 [patent_doc_number] => 20110145664 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-16 [patent_title] => 'TEST MODULE AND TEST METHOD' [patent_app_type] => utility [patent_app_number] => 13/015481 [patent_app_country] => US [patent_app_date] => 2011-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2918 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20110145664.pdf [firstpage_image] =>[orig_patent_app_number] => 13015481 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/015481
Test module and a test method for reading a number of fails for a device under test (DUT) Jan 26, 2011 Issued
Array ( [id] => 6006243 [patent_doc_number] => 20110119563 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-19 [patent_title] => 'Semiconductor memory' [patent_app_type] => utility [patent_app_number] => 12/929362 [patent_app_country] => US [patent_app_date] => 2011-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7029 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20110119563.pdf [firstpage_image] =>[orig_patent_app_number] => 12929362 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/929362
Semiconductor memory Jan 18, 2011 Abandoned
Array ( [id] => 6057532 [patent_doc_number] => 20110113306 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-12 [patent_title] => 'MEMORY DEVICE WITH ERROR DETECTION' [patent_app_type] => utility [patent_app_number] => 13/007923 [patent_app_country] => US [patent_app_date] => 2011-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1757 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20110113306.pdf [firstpage_image] =>[orig_patent_app_number] => 13007923 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/007923
Memory device with error detection Jan 16, 2011 Issued
Array ( [id] => 5990856 [patent_doc_number] => 20110099459 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-28 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/979952 [patent_app_country] => US [patent_app_date] => 2010-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 12365 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0099/20110099459.pdf [firstpage_image] =>[orig_patent_app_number] => 12979952 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/979952
SEMICONDUCTOR MEMORY DEVICE Dec 27, 2010 Abandoned
Array ( [id] => 6138482 [patent_doc_number] => 20110128044 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-02 [patent_title] => 'TEST APPARATUS, TEST METHOD, AND PHASE SHIFTER' [patent_app_type] => utility [patent_app_number] => 12/980292 [patent_app_country] => US [patent_app_date] => 2010-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5251 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20110128044.pdf [firstpage_image] =>[orig_patent_app_number] => 12980292 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/980292
TEST APPARATUS, TEST METHOD, AND PHASE SHIFTER Dec 27, 2010 Abandoned
Array ( [id] => 8297355 [patent_doc_number] => 08225156 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-07-17 [patent_title] => 'Methods and apparatuses for external voltage test methodology of input-output circuits' [patent_app_type] => utility [patent_app_number] => 12/954480 [patent_app_country] => US [patent_app_date] => 2010-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 17022 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12954480 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/954480
Methods and apparatuses for external voltage test methodology of input-output circuits Nov 23, 2010 Issued
Array ( [id] => 8787114 [patent_doc_number] => 08433969 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-04-30 [patent_title] => 'Forward error correction (FEC) auto negotiation for an optical transport network (OTN)' [patent_app_type] => utility [patent_app_number] => 12/949568 [patent_app_country] => US [patent_app_date] => 2010-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4661 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12949568 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/949568
Forward error correction (FEC) auto negotiation for an optical transport network (OTN) Nov 17, 2010 Issued
Array ( [id] => 8155436 [patent_doc_number] => 20120098435 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-26 [patent_title] => 'Channel Detection Device' [patent_app_type] => utility [patent_app_number] => 12/911065 [patent_app_country] => US [patent_app_date] => 2010-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2322 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0098/20120098435.pdf [firstpage_image] =>[orig_patent_app_number] => 12911065 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/911065
Channel detection device Oct 24, 2010 Issued
Array ( [id] => 6153917 [patent_doc_number] => 20110022905 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-27 [patent_title] => 'Test Circuit and Method for Multilevel Cell Flash Memory' [patent_app_type] => utility [patent_app_number] => 12/899120 [patent_app_country] => US [patent_app_date] => 2010-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 11312 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0022/20110022905.pdf [firstpage_image] =>[orig_patent_app_number] => 12899120 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/899120
Test circuit and method for multilevel cell flash memory Oct 5, 2010 Issued
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