Shengjun Wang

Array ( [id] => 8424724 [patent_doc_number] => 08281222 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-02 [patent_title] => 'Detection and correction of fuse re-growth in a microprocessor' [patent_app_type] => utility [patent_app_number] => 12/719307 [patent_app_country] => US [patent_app_date] => 2010-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 11919 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12719307 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8552300 [patent_doc_number] => 08327199 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-12-04 [patent_title] => 'Integrated circuit with configurable test pins' [patent_app_type] => utility [patent_app_number] => 12/718914 [patent_app_country] => US [patent_app_date] => 2010-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5641 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12718914 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6464987 [patent_doc_number] => 20100146367 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-10 [patent_title] => 'SYSTEM FOR TESTING THE UPSTREAM CHANNEL OF A CABLE NETWORK' [patent_app_type] => utility [patent_app_number] => 12/703519 [patent_app_country] => US [patent_app_date] => 2010-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4995 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0146/20100146367.pdf [firstpage_image] =>[orig_patent_app_number] => 12703519 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7679547 [patent_doc_number] => 20100107040 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-29 [patent_title] => 'APPARATUS AND METHOD FOR DEFECT REPLACEMENT' [patent_app_type] => utility [patent_app_number] => 12/652239 [patent_app_country] => US [patent_app_date] => 2010-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3113 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0107/20100107040.pdf [firstpage_image] =>[orig_patent_app_number] => 12652239 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4636994 [patent_doc_number] => 08015459 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-09-06 [patent_title] => 'Semiconductor memory device and method of performing a memory operation' [patent_app_type] => utility [patent_app_number] => 12/654644 [patent_app_country] => US [patent_app_date] => 2009-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6497 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/015/08015459.pdf [firstpage_image] =>[orig_patent_app_number] => 12654644 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4590156 [patent_doc_number] => 07831872 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-09 [patent_title] => 'Test circuit and method for multilevel cell flash memory' [patent_app_type] => utility [patent_app_number] => 12/637365 [patent_app_country] => US [patent_app_date] => 2009-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 22 [patent_no_of_words] => 11317 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/831/07831872.pdf [firstpage_image] =>[orig_patent_app_number] => 12637365 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6147491 [patent_doc_number] => 20110131477 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-02 [patent_title] => 'Systems and Methods for Analyzing and Affecting Subtle Energy' [patent_app_type] => utility [patent_app_number] => 12/628628 [patent_app_country] => US [patent_app_date] => 2009-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6889 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0131/20110131477.pdf [firstpage_image] =>[orig_patent_app_number] => 12628628 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7683906 [patent_doc_number] => 20100122235 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-13 [patent_title] => 'Method And Apparatus For Generating Self-Verifying Device Scenario Code' [patent_app_type] => utility [patent_app_number] => 12/626916 [patent_app_country] => US [patent_app_date] => 2009-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4481 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0122/20100122235.pdf [firstpage_image] =>[orig_patent_app_number] => 12626916 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6361452 [patent_doc_number] => 20100079149 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-01 [patent_title] => 'CIRCUIT TESTING APPARATUS AND SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/570885 [patent_app_country] => US [patent_app_date] => 2009-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5306 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0079/20100079149.pdf [firstpage_image] =>[orig_patent_app_number] => 12570885 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8899527 [patent_doc_number] => 08479061 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-02 [patent_title] => 'Solid state memory cartridge with wear indication' [patent_app_type] => utility [patent_app_number] => 12/566178 [patent_app_country] => US [patent_app_date] => 2009-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5791 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12566178 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8460952 [patent_doc_number] => 08296637 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-10-23 [patent_title] => 'Channel quality monitoring and method for qualifying a storage channel using an iterative decoder' [patent_app_type] => utility [patent_app_number] => 12/563964 [patent_app_country] => US [patent_app_date] => 2009-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 19 [patent_no_of_words] => 10965 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12563964 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6384756 [patent_doc_number] => 20100077280 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-25 [patent_title] => 'SEMICONDUCTOR RECORDING DEVICE' [patent_app_type] => utility [patent_app_number] => 12/563264 [patent_app_country] => US [patent_app_date] => 2009-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8870 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0077/20100077280.pdf [firstpage_image] =>[orig_patent_app_number] => 12563264 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5981886 [patent_doc_number] => 20110072328 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-24 [patent_title] => 'NONVOLATILE MEMORY CONTROLLER WITH SCALABLE PIPELINED ERROR CORRECTION' [patent_app_type] => utility [patent_app_number] => 12/563455 [patent_app_country] => US [patent_app_date] => 2009-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3937 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20110072328.pdf [firstpage_image] =>[orig_patent_app_number] => 12563455 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6512078 [patent_doc_number] => 20100095190 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-15 [patent_title] => 'STORAGE DEVICE AND DATA READING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/562699 [patent_app_country] => US [patent_app_date] => 2009-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7540 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20100095190.pdf [firstpage_image] =>[orig_patent_app_number] => 12562699 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5981922 [patent_doc_number] => 20110072335 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-24 [patent_title] => 'BRANCH-METRIC CALIBRATION USING VARYING BANDWIDTH VALUES' [patent_app_type] => utility [patent_app_number] => 12/562200 [patent_app_country] => US [patent_app_date] => 2009-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6293 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20110072335.pdf [firstpage_image] =>[orig_patent_app_number] => 12562200 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8530687 [patent_doc_number] => 08307271 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-11-06 [patent_title] => 'Fast verification of data block cycle redundancy checks' [patent_app_type] => utility [patent_app_number] => 12/586097 [patent_app_country] => US [patent_app_date] => 2009-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6642 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12586097 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4602934 [patent_doc_number] => 07979779 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-07-12 [patent_title] => 'System and method for symmetric triple parity for failing storage devices' [patent_app_type] => utility [patent_app_number] => 12/560075 [patent_app_country] => US [patent_app_date] => 2009-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10166 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/979/07979779.pdf [firstpage_image] =>[orig_patent_app_number] => 12560075 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7547978 [patent_doc_number] => 08055959 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-08 [patent_title] => 'Disabling faulty flash memory dies' [patent_app_type] => utility [patent_app_number] => 12/559341 [patent_app_country] => US [patent_app_date] => 2009-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 8159 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/055/08055959.pdf [firstpage_image] =>[orig_patent_app_number] => 12559341 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6008923 [patent_doc_number] => 20110060955 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-10 [patent_title] => 'METHOD AND APPARATUS FOR PROVIDING FREQUENCY ERROR ESTIMATION' [patent_app_type] => utility [patent_app_number] => 12/554598 [patent_app_country] => US [patent_app_date] => 2009-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5526 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0060/20110060955.pdf [firstpage_image] =>[orig_patent_app_number] => 12554598 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6227782 [patent_doc_number] => 20100058136 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-04 [patent_title] => 'System and Method for Rate Matching to Enhance System Throughput Based on Packet Size' [patent_app_type] => utility [patent_app_number] => 12/554742 [patent_app_country] => US [patent_app_date] => 2009-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5313 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0058/20100058136.pdf [firstpage_image] =>[orig_patent_app_number] => 12554742 [rel_patent_id] =>[rel_patent_doc_number] =>)