Search

Shengjun Wang

Examiner (ID: 18947, Phone: (571)272-0632 , Office: P/1627 )

Most Active Art Unit
1627
Art Unit(s)
1627, 1617
Total Applications
2559
Issued Applications
1079
Pending Applications
238
Abandoned Applications
1248

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5266880 [patent_doc_number] => 20090119565 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-07 [patent_title] => 'Data transmitting/receiving system and method thereof' [patent_app_type] => utility [patent_app_number] => 12/318262 [patent_app_country] => US [patent_app_date] => 2008-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6261 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20090119565.pdf [firstpage_image] =>[orig_patent_app_number] => 12318262 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/318262
Data transmitting/receiving system and method thereof Dec 22, 2008 Issued
Array ( [id] => 5499856 [patent_doc_number] => 20090160544 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-25 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/342015 [patent_app_country] => US [patent_app_date] => 2008-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 7549 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0160/20090160544.pdf [firstpage_image] =>[orig_patent_app_number] => 12342015 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/342015
Semiconductor integrated circuit including power domains Dec 21, 2008 Issued
Array ( [id] => 6302409 [patent_doc_number] => 20100162058 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-24 [patent_title] => 'SEQUENTIAL ELEMENT LOW POWER SCAN IMPLEMENTATION' [patent_app_type] => utility [patent_app_number] => 12/341825 [patent_app_country] => US [patent_app_date] => 2008-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2594 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0162/20100162058.pdf [firstpage_image] =>[orig_patent_app_number] => 12341825 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/341825
Sequential element low power scan implementation Dec 21, 2008 Issued
Array ( [id] => 5286624 [patent_doc_number] => 20090100299 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-16 [patent_title] => 'Methods and Apparatus for Patternizing Device Responses' [patent_app_type] => utility [patent_app_number] => 12/338065 [patent_app_country] => US [patent_app_date] => 2008-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 5879 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0100/20090100299.pdf [firstpage_image] =>[orig_patent_app_number] => 12338065 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/338065
Methods and apparatus for patternizing device responses Dec 17, 2008 Issued
Array ( [id] => 5442864 [patent_doc_number] => 20090094503 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-09 [patent_title] => 'FAST H-ARQ ACKNOWLEDGEMENT GENERATION METHOD USING A STOPPING RULE FOR TURBO DECODING' [patent_app_type] => utility [patent_app_number] => 12/335167 [patent_app_country] => US [patent_app_date] => 2008-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2737 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20090094503.pdf [firstpage_image] =>[orig_patent_app_number] => 12335167 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/335167
Fast H-ARQ acknowledgement generation method using a stopping rule for turbo decoding Dec 14, 2008 Issued
Array ( [id] => 4642035 [patent_doc_number] => 08020070 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-09-13 [patent_title] => 'Trapping set decoding for transmission frames' [patent_app_type] => utility [patent_app_number] => 12/329514 [patent_app_country] => US [patent_app_date] => 2008-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4087 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/020/08020070.pdf [firstpage_image] =>[orig_patent_app_number] => 12329514 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/329514
Trapping set decoding for transmission frames Dec 4, 2008 Issued
Array ( [id] => 5548224 [patent_doc_number] => 20090158101 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-18 [patent_title] => 'Adapting Word Line Pulse Widths in Memory Systems' [patent_app_type] => utility [patent_app_number] => 12/328156 [patent_app_country] => US [patent_app_date] => 2008-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5425 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0158/20090158101.pdf [firstpage_image] =>[orig_patent_app_number] => 12328156 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/328156
Adapting word line pulse widths in memory systems Dec 3, 2008 Issued
Array ( [id] => 7972265 [patent_doc_number] => 07941711 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-10 [patent_title] => 'Determining bit error rate using single data burst' [patent_app_type] => utility [patent_app_number] => 12/328409 [patent_app_country] => US [patent_app_date] => 2008-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2630 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/941/07941711.pdf [firstpage_image] =>[orig_patent_app_number] => 12328409 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/328409
Determining bit error rate using single data burst Dec 3, 2008 Issued
Array ( [id] => 5344388 [patent_doc_number] => 20090183038 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-16 [patent_title] => 'METHOD FOR IMPROVING THE INTEGRITY OF COMMUNICATION MEANS' [patent_app_type] => utility [patent_app_number] => 12/328193 [patent_app_country] => US [patent_app_date] => 2008-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4697 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0183/20090183038.pdf [firstpage_image] =>[orig_patent_app_number] => 12328193 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/328193
Method for improving the integrity of communication means Dec 3, 2008 Issued
Array ( [id] => 7982739 [patent_doc_number] => 08074128 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-12-06 [patent_title] => 'Block management and replacement method, flash memory storage system and controller using the same' [patent_app_type] => utility [patent_app_number] => 12/328467 [patent_app_country] => US [patent_app_date] => 2008-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6901 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/074/08074128.pdf [firstpage_image] =>[orig_patent_app_number] => 12328467 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/328467
Block management and replacement method, flash memory storage system and controller using the same Dec 3, 2008 Issued
Array ( [id] => 6610982 [patent_doc_number] => 20100131812 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-27 [patent_title] => 'Resizable Cache Memory' [patent_app_type] => utility [patent_app_number] => 12/323932 [patent_app_country] => US [patent_app_date] => 2008-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6140 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0131/20100131812.pdf [firstpage_image] =>[orig_patent_app_number] => 12323932 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/323932
System and method including built-in self test (BIST) circuit to test cache memory Nov 25, 2008 Issued
Array ( [id] => 5565914 [patent_doc_number] => 20090138767 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-28 [patent_title] => 'Self-diagnostic circuit and self-diagnostic method for detecting errors' [patent_app_type] => utility [patent_app_number] => 12/292862 [patent_app_country] => US [patent_app_date] => 2008-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4770 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20090138767.pdf [firstpage_image] =>[orig_patent_app_number] => 12292862 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/292862
Self-diagnostic circuit and self-diagnostic method for detecting errors Nov 25, 2008 Issued
Array ( [id] => 6610928 [patent_doc_number] => 20100131808 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-27 [patent_title] => 'Method For Testing Memory' [patent_app_type] => utility [patent_app_number] => 12/277463 [patent_app_country] => US [patent_app_date] => 2008-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1916 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0131/20100131808.pdf [firstpage_image] =>[orig_patent_app_number] => 12277463 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/277463
Method For Testing Memory Nov 24, 2008 Abandoned
Array ( [id] => 5387494 [patent_doc_number] => 20090228739 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-10 [patent_title] => 'RECOVERY WHILE PROGRAMMING NON-VOLATILE MEMORY (NVM)' [patent_app_type] => utility [patent_app_number] => 12/323333 [patent_app_country] => US [patent_app_date] => 2008-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 24297 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0228/20090228739.pdf [firstpage_image] =>[orig_patent_app_number] => 12323333 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/323333
Recovery while programming non-volatile memory (NVM) Nov 24, 2008 Issued
Array ( [id] => 5339232 [patent_doc_number] => 20090055696 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-26 [patent_title] => 'MICROCONTROLLER FOR LOGIC BUILT-IN SELF TEST (LBIST)' [patent_app_type] => utility [patent_app_number] => 12/268583 [patent_app_country] => US [patent_app_date] => 2008-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4888 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20090055696.pdf [firstpage_image] =>[orig_patent_app_number] => 12268583 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/268583
Microcontroller for logic built-in self test (LBIST) Nov 10, 2008 Issued
Array ( [id] => 175659 [patent_doc_number] => 07661042 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-09 [patent_title] => 'Low-power content-addressable-memory device' [patent_app_type] => utility [patent_app_number] => 12/265869 [patent_app_country] => US [patent_app_date] => 2008-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 32 [patent_no_of_words] => 15830 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/661/07661042.pdf [firstpage_image] =>[orig_patent_app_number] => 12265869 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/265869
Low-power content-addressable-memory device Nov 5, 2008 Issued
Array ( [id] => 8235593 [patent_doc_number] => 08201057 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-06-12 [patent_title] => 'System and method for inter-packet channel coding and decoding' [patent_app_type] => utility [patent_app_number] => 12/285929 [patent_app_country] => US [patent_app_date] => 2008-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 7133 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/201/08201057.pdf [firstpage_image] =>[orig_patent_app_number] => 12285929 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/285929
System and method for inter-packet channel coding and decoding Oct 15, 2008 Issued
Array ( [id] => 5418174 [patent_doc_number] => 20090044061 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-12 [patent_title] => 'STRUCTURE AND METHOD FOR DETECTING ERRORS IN A MULTILEVEL MEMORY DEVICE WITH IMPROVED PROGRAMMING GRANULARITY' [patent_app_type] => utility [patent_app_number] => 12/251289 [patent_app_country] => US [patent_app_date] => 2008-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4962 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0044/20090044061.pdf [firstpage_image] =>[orig_patent_app_number] => 12251289 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/251289
Structure and method for detecting errors in a multilevel memory device with improved programming granularity Oct 13, 2008 Issued
Array ( [id] => 5358579 [patent_doc_number] => 20090033373 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-05 [patent_title] => 'Circuit and Method for Trimming Integrated Circuits' [patent_app_type] => utility [patent_app_number] => 12/248915 [patent_app_country] => US [patent_app_date] => 2008-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7867 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0033/20090033373.pdf [firstpage_image] =>[orig_patent_app_number] => 12248915 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/248915
Circuit and Method for Trimming Integrated Circuits Oct 9, 2008 Abandoned
Array ( [id] => 4462603 [patent_doc_number] => 07895489 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-22 [patent_title] => 'Matrix system and method for debugging scan structure' [patent_app_type] => utility [patent_app_number] => 12/249317 [patent_app_country] => US [patent_app_date] => 2008-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 5770 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 312 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/895/07895489.pdf [firstpage_image] =>[orig_patent_app_number] => 12249317 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/249317
Matrix system and method for debugging scan structure Oct 9, 2008 Issued
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