
Shengjun Wang
Examiner (ID: 18947, Phone: (571)272-0632 , Office: P/1627 )
| Most Active Art Unit | 1627 |
| Art Unit(s) | 1627, 1617 |
| Total Applications | 2559 |
| Issued Applications | 1079 |
| Pending Applications | 238 |
| Abandoned Applications | 1248 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5266880
[patent_doc_number] => 20090119565
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-05-07
[patent_title] => 'Data transmitting/receiving system and method thereof'
[patent_app_type] => utility
[patent_app_number] => 12/318262
[patent_app_country] => US
[patent_app_date] => 2008-12-23
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[pdf_file] => publications/A1/0119/20090119565.pdf
[firstpage_image] =>[orig_patent_app_number] => 12318262
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/318262 | Data transmitting/receiving system and method thereof | Dec 22, 2008 | Issued |
Array
(
[id] => 5499856
[patent_doc_number] => 20090160544
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-06-25
[patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT'
[patent_app_type] => utility
[patent_app_number] => 12/342015
[patent_app_country] => US
[patent_app_date] => 2008-12-22
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 12342015
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/342015 | Semiconductor integrated circuit including power domains | Dec 21, 2008 | Issued |
Array
(
[id] => 6302409
[patent_doc_number] => 20100162058
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-06-24
[patent_title] => 'SEQUENTIAL ELEMENT LOW POWER SCAN IMPLEMENTATION'
[patent_app_type] => utility
[patent_app_number] => 12/341825
[patent_app_country] => US
[patent_app_date] => 2008-12-22
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[pdf_file] => publications/A1/0162/20100162058.pdf
[firstpage_image] =>[orig_patent_app_number] => 12341825
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/341825 | Sequential element low power scan implementation | Dec 21, 2008 | Issued |
Array
(
[id] => 5286624
[patent_doc_number] => 20090100299
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-04-16
[patent_title] => 'Methods and Apparatus for Patternizing Device Responses'
[patent_app_type] => utility
[patent_app_number] => 12/338065
[patent_app_country] => US
[patent_app_date] => 2008-12-18
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/338065 | Methods and apparatus for patternizing device responses | Dec 17, 2008 | Issued |
Array
(
[id] => 5442864
[patent_doc_number] => 20090094503
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[patent_kind] => A1
[patent_issue_date] => 2009-04-09
[patent_title] => 'FAST H-ARQ ACKNOWLEDGEMENT GENERATION METHOD USING A STOPPING RULE FOR TURBO DECODING'
[patent_app_type] => utility
[patent_app_number] => 12/335167
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[patent_app_date] => 2008-12-15
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[firstpage_image] =>[orig_patent_app_number] => 12335167
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/335167 | Fast H-ARQ acknowledgement generation method using a stopping rule for turbo decoding | Dec 14, 2008 | Issued |
Array
(
[id] => 4642035
[patent_doc_number] => 08020070
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-09-13
[patent_title] => 'Trapping set decoding for transmission frames'
[patent_app_type] => utility
[patent_app_number] => 12/329514
[patent_app_country] => US
[patent_app_date] => 2008-12-05
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/329514 | Trapping set decoding for transmission frames | Dec 4, 2008 | Issued |
Array
(
[id] => 5548224
[patent_doc_number] => 20090158101
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[patent_kind] => A1
[patent_issue_date] => 2009-06-18
[patent_title] => 'Adapting Word Line Pulse Widths in Memory Systems'
[patent_app_type] => utility
[patent_app_number] => 12/328156
[patent_app_country] => US
[patent_app_date] => 2008-12-04
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 12328156
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/328156 | Adapting word line pulse widths in memory systems | Dec 3, 2008 | Issued |
Array
(
[id] => 7972265
[patent_doc_number] => 07941711
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-05-10
[patent_title] => 'Determining bit error rate using single data burst'
[patent_app_type] => utility
[patent_app_number] => 12/328409
[patent_app_country] => US
[patent_app_date] => 2008-12-04
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[pdf_file] => patents/07/941/07941711.pdf
[firstpage_image] =>[orig_patent_app_number] => 12328409
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/328409 | Determining bit error rate using single data burst | Dec 3, 2008 | Issued |
Array
(
[id] => 5344388
[patent_doc_number] => 20090183038
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-07-16
[patent_title] => 'METHOD FOR IMPROVING THE INTEGRITY OF COMMUNICATION MEANS'
[patent_app_type] => utility
[patent_app_number] => 12/328193
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[patent_app_date] => 2008-12-04
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[firstpage_image] =>[orig_patent_app_number] => 12328193
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/328193 | Method for improving the integrity of communication means | Dec 3, 2008 | Issued |
Array
(
[id] => 7982739
[patent_doc_number] => 08074128
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-12-06
[patent_title] => 'Block management and replacement method, flash memory storage system and controller using the same'
[patent_app_type] => utility
[patent_app_number] => 12/328467
[patent_app_country] => US
[patent_app_date] => 2008-12-04
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[pdf_file] => patents/08/074/08074128.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/328467 | Block management and replacement method, flash memory storage system and controller using the same | Dec 3, 2008 | Issued |
Array
(
[id] => 6610982
[patent_doc_number] => 20100131812
[patent_country] => US
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[patent_issue_date] => 2010-05-27
[patent_title] => 'Resizable Cache Memory'
[patent_app_type] => utility
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[firstpage_image] =>[orig_patent_app_number] => 12323932
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/323932 | System and method including built-in self test (BIST) circuit to test cache memory | Nov 25, 2008 | Issued |
Array
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[id] => 5565914
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[patent_title] => 'Self-diagnostic circuit and self-diagnostic method for detecting errors'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/292862 | Self-diagnostic circuit and self-diagnostic method for detecting errors | Nov 25, 2008 | Issued |
Array
(
[id] => 6610928
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[patent_title] => 'Method For Testing Memory'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/277463 | Method For Testing Memory | Nov 24, 2008 | Abandoned |
Array
(
[id] => 5387494
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[patent_title] => 'RECOVERY WHILE PROGRAMMING NON-VOLATILE MEMORY (NVM)'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/323333 | Recovery while programming non-volatile memory (NVM) | Nov 24, 2008 | Issued |
Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/268583 | Microcontroller for logic built-in self test (LBIST) | Nov 10, 2008 | Issued |
Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/265869 | Low-power content-addressable-memory device | Nov 5, 2008 | Issued |
Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/251289 | Structure and method for detecting errors in a multilevel memory device with improved programming granularity | Oct 13, 2008 | Issued |
Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/249317 | Matrix system and method for debugging scan structure | Oct 9, 2008 | Issued |