
Shengjun Wang
Examiner (ID: 18947, Phone: (571)272-0632 , Office: P/1627 )
| Most Active Art Unit | 1627 |
| Art Unit(s) | 1627, 1617 |
| Total Applications | 2559 |
| Issued Applications | 1079 |
| Pending Applications | 238 |
| Abandoned Applications | 1248 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5286635
[patent_doc_number] => 20090100310
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-04-16
[patent_title] => 'Apparatus and method for hybrid automatic repeat request (HARQ) in wireless communication system'
[patent_app_type] => utility
[patent_app_number] => 12/287310
[patent_app_country] => US
[patent_app_date] => 2008-10-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4015
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0100/20090100310.pdf
[firstpage_image] =>[orig_patent_app_number] => 12287310
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/287310 | Apparatus and method for hybrid automatic repeat request (HARQ) in wireless communication system | Oct 7, 2008 | Issued |
Array
(
[id] => 7679566
[patent_doc_number] => 20100107021
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-04-29
[patent_title] => 'SEMICONDUCTOR MEMORY DEVICE'
[patent_app_type] => utility
[patent_app_number] => 12/523607
[patent_app_country] => US
[patent_app_date] => 2008-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 5319
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0107/20100107021.pdf
[firstpage_image] =>[orig_patent_app_number] => 12523607
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/523607 | Semiconductor memory device with error correction | Sep 29, 2008 | Issued |
Array
(
[id] => 9507148
[patent_doc_number] => 08745471
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-06-03
[patent_title] => 'Low-density parity-check convolutional code (LDPC-CC) encoding method, encoder and decoder'
[patent_app_type] => utility
[patent_app_number] => 12/679740
[patent_app_country] => US
[patent_app_date] => 2008-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 75
[patent_figures_cnt] => 82
[patent_no_of_words] => 77373
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12679740
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/679740 | Low-density parity-check convolutional code (LDPC-CC) encoding method, encoder and decoder | Sep 25, 2008 | Issued |
Array
(
[id] => 5430327
[patent_doc_number] => 20090089637
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-04-02
[patent_title] => 'Semiconductor test system and test method thereof'
[patent_app_type] => utility
[patent_app_number] => 12/285003
[patent_app_country] => US
[patent_app_date] => 2008-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 7514
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0089/20090089637.pdf
[firstpage_image] =>[orig_patent_app_number] => 12285003
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/285003 | Semiconductor test system and test method thereof | Sep 25, 2008 | Abandoned |
Array
(
[id] => 4550075
[patent_doc_number] => 07925939
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-04-12
[patent_title] => 'Pre-code device, and pre-code system and pre-coding method thererof'
[patent_app_type] => utility
[patent_app_number] => 12/238719
[patent_app_country] => US
[patent_app_date] => 2008-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 2910
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 67
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/925/07925939.pdf
[firstpage_image] =>[orig_patent_app_number] => 12238719
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/238719 | Pre-code device, and pre-code system and pre-coding method thererof | Sep 25, 2008 | Issued |
Array
(
[id] => 5283670
[patent_doc_number] => 20090097344
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-04-16
[patent_title] => 'SEMICONDUCTOR MEMORY TESTING DEVICE AND METHOD OF TESTING SEMICONDUCTOR USING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 12/205036
[patent_app_country] => US
[patent_app_date] => 2008-09-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 6330
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0097/20090097344.pdf
[firstpage_image] =>[orig_patent_app_number] => 12205036
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/205036 | Semiconductor memory testing device and method of testing semiconductor using the same | Sep 4, 2008 | Issued |
Array
(
[id] => 4854608
[patent_doc_number] => 20080320351
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-12-25
[patent_title] => 'LOW POWER SCAN & DELAY TEST METHOD AND APPARATUS'
[patent_app_type] => utility
[patent_app_number] => 12/204267
[patent_app_country] => US
[patent_app_date] => 2008-09-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3604
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0320/20080320351.pdf
[firstpage_image] =>[orig_patent_app_number] => 12204267
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/204267 | Segmented scan paths with cache bit memory inputs | Sep 3, 2008 | Issued |
Array
(
[id] => 7768322
[patent_doc_number] => 08117509
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-02-14
[patent_title] => 'Memory control circuit, semiconductor integrated circuit, and verification method of nonvolatile memory'
[patent_app_type] => utility
[patent_app_number] => 12/230683
[patent_app_country] => US
[patent_app_date] => 2008-09-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 17
[patent_no_of_words] => 7553
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/117/08117509.pdf
[firstpage_image] =>[orig_patent_app_number] => 12230683
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/230683 | Memory control circuit, semiconductor integrated circuit, and verification method of nonvolatile memory | Sep 2, 2008 | Issued |
Array
(
[id] => 5273568
[patent_doc_number] => 20090077344
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-03-19
[patent_title] => 'Method for bus testing and addressing in mass memory components'
[patent_app_type] => utility
[patent_app_number] => 12/231329
[patent_app_country] => US
[patent_app_date] => 2008-08-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 5143
[patent_no_of_claims] => 36
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0077/20090077344.pdf
[firstpage_image] =>[orig_patent_app_number] => 12231329
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/231329 | Method for bus testing and addressing in mass memory components | Aug 27, 2008 | Abandoned |
Array
(
[id] => 4637007
[patent_doc_number] => 08015472
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2011-09-06
[patent_title] => 'Triple parity technique for enabling efficient recovery from triple failures in a storage array'
[patent_app_type] => utility
[patent_app_number] => 12/195968
[patent_app_country] => US
[patent_app_date] => 2008-08-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 16006
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 169
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/015/08015472.pdf
[firstpage_image] =>[orig_patent_app_number] => 12195968
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/195968 | Triple parity technique for enabling efficient recovery from triple failures in a storage array | Aug 20, 2008 | Issued |
Array
(
[id] => 4527968
[patent_doc_number] => 07934135
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-04-26
[patent_title] => 'Providing pseudo-randomized static values during LBIST transition tests'
[patent_app_type] => utility
[patent_app_number] => 12/195641
[patent_app_country] => US
[patent_app_date] => 2008-08-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3505
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 149
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/934/07934135.pdf
[firstpage_image] =>[orig_patent_app_number] => 12195641
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/195641 | Providing pseudo-randomized static values during LBIST transition tests | Aug 20, 2008 | Issued |
Array
(
[id] => 6648259
[patent_doc_number] => 20100037111
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-02-11
[patent_title] => 'METHOD AND APPARATUS FOR TESTING DELAY FAULTS'
[patent_app_type] => utility
[patent_app_number] => 12/187145
[patent_app_country] => US
[patent_app_date] => 2008-08-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4932
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0037/20100037111.pdf
[firstpage_image] =>[orig_patent_app_number] => 12187145
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/187145 | Method and apparatus for testing delay faults | Aug 5, 2008 | Issued |
Array
(
[id] => 237745
[patent_doc_number] => 07596734
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-09-29
[patent_title] => 'On-Chip AC self-test controller'
[patent_app_type] => utility
[patent_app_number] => 12/185172
[patent_app_country] => US
[patent_app_date] => 2008-08-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3832
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 172
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/596/07596734.pdf
[firstpage_image] =>[orig_patent_app_number] => 12185172
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/185172 | On-Chip AC self-test controller | Aug 3, 2008 | Issued |
Array
(
[id] => 6262976
[patent_doc_number] => 20100031096
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-02-04
[patent_title] => 'INTERNAL FAIL BIT OR BYTE COUNTER'
[patent_app_type] => utility
[patent_app_number] => 12/184002
[patent_app_country] => US
[patent_app_date] => 2008-07-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 4665
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0031/20100031096.pdf
[firstpage_image] =>[orig_patent_app_number] => 12184002
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/184002 | INTERNAL FAIL BIT OR BYTE COUNTER | Jul 30, 2008 | Abandoned |
Array
(
[id] => 7680988
[patent_doc_number] => 20100023820
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-01-28
[patent_title] => 'Asynchronous Communication Apparatus Using JTAG Test Data Registers'
[patent_app_type] => utility
[patent_app_number] => 12/178776
[patent_app_country] => US
[patent_app_date] => 2008-07-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3716
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0023/20100023820.pdf
[firstpage_image] =>[orig_patent_app_number] => 12178776
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/178776 | Asynchronous communication apparatus using JTAG test data registers | Jul 23, 2008 | Issued |
Array
(
[id] => 4948205
[patent_doc_number] => 20080304331
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-12-11
[patent_title] => 'Semiconductor integrated circuit with full-speed data transition scheme for DDR SDRAM at internally doubled clock testing application'
[patent_app_type] => utility
[patent_app_number] => 12/220062
[patent_app_country] => US
[patent_app_date] => 2008-07-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 2682
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0304/20080304331.pdf
[firstpage_image] =>[orig_patent_app_number] => 12220062
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/220062 | Semiconductor integrated circuit with full-speed data transition scheme for DDR SDRAM at internally doubled clock testing application | Jul 20, 2008 | Issued |
Array
(
[id] => 220466
[patent_doc_number] => 07613962
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-11-03
[patent_title] => 'Semiconductor integrated circuit with full-speed data transition scheme for DDR SDRAM at internally doubled clock testing application'
[patent_app_type] => utility
[patent_app_number] => 12/220063
[patent_app_country] => US
[patent_app_date] => 2008-07-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 9
[patent_no_of_words] => 2691
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 214
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/613/07613962.pdf
[firstpage_image] =>[orig_patent_app_number] => 12220063
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/220063 | Semiconductor integrated circuit with full-speed data transition scheme for DDR SDRAM at internally doubled clock testing application | Jul 20, 2008 | Issued |
Array
(
[id] => 163399
[patent_doc_number] => 07676708
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-03-09
[patent_title] => 'Semiconductor integrated circuit with full-speed data transition scheme for DDR SDRAM at internally doubled clock testing application'
[patent_app_type] => utility
[patent_app_number] => 12/220034
[patent_app_country] => US
[patent_app_date] => 2008-07-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 9
[patent_no_of_words] => 2690
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 220
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/676/07676708.pdf
[firstpage_image] =>[orig_patent_app_number] => 12220034
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/220034 | Semiconductor integrated circuit with full-speed data transition scheme for DDR SDRAM at internally doubled clock testing application | Jul 20, 2008 | Issued |
Array
(
[id] => 5568667
[patent_doc_number] => 20090252045
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-10-08
[patent_title] => 'NETWORK SYSTEM'
[patent_app_type] => utility
[patent_app_number] => 12/175974
[patent_app_country] => US
[patent_app_date] => 2008-07-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 5708
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0252/20090252045.pdf
[firstpage_image] =>[orig_patent_app_number] => 12175974
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/175974 | Network system for diagnosing operational abnormality of nodes | Jul 17, 2008 | Issued |
Array
(
[id] => 4530786
[patent_doc_number] => 07913134
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-03-22
[patent_title] => 'Test circuit capable of sequentially performing boundary scan test and test method thereof'
[patent_app_type] => utility
[patent_app_number] => 12/172894
[patent_app_country] => US
[patent_app_date] => 2008-07-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 3898
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 146
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/913/07913134.pdf
[firstpage_image] =>[orig_patent_app_number] => 12172894
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/172894 | Test circuit capable of sequentially performing boundary scan test and test method thereof | Jul 13, 2008 | Issued |