Search

Shengjun Wang

Examiner (ID: 18947, Phone: (571)272-0632 , Office: P/1627 )

Most Active Art Unit
1627
Art Unit(s)
1627, 1617
Total Applications
2559
Issued Applications
1079
Pending Applications
238
Abandoned Applications
1248

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 156292 [patent_doc_number] => 07681095 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-16 [patent_title] => 'Methods and apparatus for testing integrated circuits' [patent_app_type] => utility [patent_app_number] => 12/170213 [patent_app_country] => US [patent_app_date] => 2008-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4711 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/681/07681095.pdf [firstpage_image] =>[orig_patent_app_number] => 12170213 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/170213
Methods and apparatus for testing integrated circuits Jul 8, 2008 Issued
Array ( [id] => 4862464 [patent_doc_number] => 20080270863 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-30 [patent_title] => 'METHODS OF SYNCHRONOUS DIGITAL OPERATION AND SCAN BASED TESTING OF AN INTEGRATED CIRCUIT USING NEGATIVE EDGE FLIP-FLOPS FOR MUXSCAN AND EDGE CLOCK COMPATIBLE LSSD' [patent_app_type] => utility [patent_app_number] => 12/168210 [patent_app_country] => US [patent_app_date] => 2008-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3107 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0270/20080270863.pdf [firstpage_image] =>[orig_patent_app_number] => 12168210 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/168210
METHODS OF SYNCHRONOUS DIGITAL OPERATION AND SCAN BASED TESTING OF AN INTEGRATED CIRCUIT USING NEGATIVE EDGE FLIP-FLOPS FOR MUXSCAN AND EDGE CLOCK COMPATIBLE LSSD Jul 6, 2008 Abandoned
Array ( [id] => 5363004 [patent_doc_number] => 20090037798 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-05 [patent_title] => 'SELF-RESETTING, SELF-CORRECTING LATCHES' [patent_app_type] => utility [patent_app_number] => 12/168142 [patent_app_country] => US [patent_app_date] => 2008-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5037 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20090037798.pdf [firstpage_image] =>[orig_patent_app_number] => 12168142 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/168142
Self-resetting, self-correcting latches Jul 5, 2008 Issued
Array ( [id] => 245163 [patent_doc_number] => 07590907 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-15 [patent_title] => 'Method and apparatus for soft-error immune and self-correcting latches' [patent_app_type] => utility [patent_app_number] => 12/168147 [patent_app_country] => US [patent_app_date] => 2008-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3127 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/590/07590907.pdf [firstpage_image] =>[orig_patent_app_number] => 12168147 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/168147
Method and apparatus for soft-error immune and self-correcting latches Jul 5, 2008 Issued
Array ( [id] => 4862458 [patent_doc_number] => 20080270861 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-30 [patent_title] => 'NEGATIVE EDGE FLIP-FLOPS FOR MUXSCAN AND EDGE CLOCK COMPATIBLE LSSD' [patent_app_type] => utility [patent_app_number] => 12/167470 [patent_app_country] => US [patent_app_date] => 2008-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3107 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0270/20080270861.pdf [firstpage_image] =>[orig_patent_app_number] => 12167470 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/167470
NEGATIVE EDGE FLIP-FLOPS FOR MUXSCAN AND EDGE CLOCK COMPATIBLE LSSD Jul 2, 2008 Abandoned
Array ( [id] => 7537698 [patent_doc_number] => 08051341 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-01 [patent_title] => 'Semiconductor memory device having test address generating circuit and method of testing semiconductor memory device having a test address generating circuit' [patent_app_type] => utility [patent_app_number] => 12/214453 [patent_app_country] => US [patent_app_date] => 2008-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5981 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/051/08051341.pdf [firstpage_image] =>[orig_patent_app_number] => 12214453 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/214453
Semiconductor memory device having test address generating circuit and method of testing semiconductor memory device having a test address generating circuit Jun 18, 2008 Issued
Array ( [id] => 4487112 [patent_doc_number] => 07870454 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-11 [patent_title] => 'Structure for system for and method of performing high speed memory diagnostics via built-in-self-test' [patent_app_type] => utility [patent_app_number] => 12/126452 [patent_app_country] => US [patent_app_date] => 2008-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5226 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/870/07870454.pdf [firstpage_image] =>[orig_patent_app_number] => 12126452 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/126452
Structure for system for and method of performing high speed memory diagnostics via built-in-self-test May 22, 2008 Issued
Array ( [id] => 5387506 [patent_doc_number] => 20090228751 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-10 [patent_title] => ' METHOD FOR PERFORMING LOGIC BUILT-IN-SELF-TEST CYCLES ON A SEMICONDUCTOR CHIP AND A CORRESPONDING SEMICONDUCTOR CHIP WITH A TEST ENGINE' [patent_app_type] => utility [patent_app_number] => 12/125476 [patent_app_country] => US [patent_app_date] => 2008-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3752 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0228/20090228751.pdf [firstpage_image] =>[orig_patent_app_number] => 12125476 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/125476
METHOD FOR PERFORMING LOGIC BUILT-IN-SELF-TEST CYCLES ON A SEMICONDUCTOR CHIP AND A CORRESPONDING SEMICONDUCTOR CHIP WITH A TEST ENGINE May 21, 2008 Abandoned
Array ( [id] => 8011015 [patent_doc_number] => 08086925 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-12-27 [patent_title] => 'Method and system for LBIST testing of an electronic circuit' [patent_app_type] => utility [patent_app_number] => 12/123540 [patent_app_country] => US [patent_app_date] => 2008-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6065 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/086/08086925.pdf [firstpage_image] =>[orig_patent_app_number] => 12123540 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/123540
Method and system for LBIST testing of an electronic circuit May 19, 2008 Issued
Array ( [id] => 7595717 [patent_doc_number] => 07620865 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-11-17 [patent_title] => 'Scan string segmentation for digital test compression' [patent_app_type] => utility [patent_app_number] => 12/120787 [patent_app_country] => US [patent_app_date] => 2008-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3828 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/620/07620865.pdf [firstpage_image] =>[orig_patent_app_number] => 12120787 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/120787
Scan string segmentation for digital test compression May 14, 2008 Issued
Array ( [id] => 4793843 [patent_doc_number] => 20080294817 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-27 [patent_title] => 'DATA TRANSMITTING APPARATUS' [patent_app_type] => utility [patent_app_number] => 12/118892 [patent_app_country] => US [patent_app_date] => 2008-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4724 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0294/20080294817.pdf [firstpage_image] =>[orig_patent_app_number] => 12118892 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/118892
DATA TRANSMITTING APPARATUS May 11, 2008 Abandoned
Array ( [id] => 171933 [patent_doc_number] => 07669101 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-23 [patent_title] => 'Methods for distributing programs for generating test data' [patent_app_type] => utility [patent_app_number] => 12/117701 [patent_app_country] => US [patent_app_date] => 2008-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 23 [patent_no_of_words] => 14271 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/669/07669101.pdf [firstpage_image] =>[orig_patent_app_number] => 12117701 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/117701
Methods for distributing programs for generating test data May 7, 2008 Issued
Array ( [id] => 4587018 [patent_doc_number] => 07849385 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-07 [patent_title] => 'Systems and methods for media defect detection utilizing correlated DFIR and LLR data' [patent_app_type] => utility [patent_app_number] => 12/111255 [patent_app_country] => US [patent_app_date] => 2008-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6062 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/849/07849385.pdf [firstpage_image] =>[orig_patent_app_number] => 12111255 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/111255
Systems and methods for media defect detection utilizing correlated DFIR and LLR data Apr 28, 2008 Issued
Array ( [id] => 4841623 [patent_doc_number] => 20080282109 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-13 [patent_title] => 'Debugging system and debugging method' [patent_app_type] => utility [patent_app_number] => 12/149244 [patent_app_country] => US [patent_app_date] => 2008-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3173 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0282/20080282109.pdf [firstpage_image] =>[orig_patent_app_number] => 12149244 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/149244
Debugging system and method including an emulator for debugging a target device Apr 28, 2008 Issued
Array ( [id] => 4888966 [patent_doc_number] => 20080263298 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-23 [patent_title] => 'Semiconductor device controlling debug operation of processing unit in response to permission or prohibition from other processing unit' [patent_app_type] => utility [patent_app_number] => 12/081823 [patent_app_country] => US [patent_app_date] => 2008-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6514 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0263/20080263298.pdf [firstpage_image] =>[orig_patent_app_number] => 12081823 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/081823
Semiconductor device controlling debug operation of processing unit in response to permission or prohibition from other processing unit Apr 21, 2008 Issued
Array ( [id] => 5497568 [patent_doc_number] => 20090265596 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-22 [patent_title] => 'SEMICONDUCTOR DEVICES, INTEGRATED CIRCUIT PACKAGES AND TESTING METHODS THEREOF' [patent_app_type] => utility [patent_app_number] => 12/107166 [patent_app_country] => US [patent_app_date] => 2008-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6483 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0265/20090265596.pdf [firstpage_image] =>[orig_patent_app_number] => 12107166 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/107166
SEMICONDUCTOR DEVICES, INTEGRATED CIRCUIT PACKAGES AND TESTING METHODS THEREOF Apr 21, 2008 Abandoned
Array ( [id] => 106997 [patent_doc_number] => 07730376 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-01 [patent_title] => 'Providing high availability in a PCI-Express™ link in the presence of lane faults' [patent_app_type] => utility [patent_app_number] => 12/056777 [patent_app_country] => US [patent_app_date] => 2008-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3042 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/730/07730376.pdf [firstpage_image] =>[orig_patent_app_number] => 12056777 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/056777
Providing high availability in a PCI-Expressâ„¢ link in the presence of lane faults Mar 26, 2008 Issued
Array ( [id] => 5405680 [patent_doc_number] => 20090240995 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-24 [patent_title] => 'METHOD AND APPARATUS FOR IMPROVING RANDOM PATTERN TESTING OF LOGIC STRUCTURES' [patent_app_type] => utility [patent_app_number] => 12/051744 [patent_app_country] => US [patent_app_date] => 2008-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 3318 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0240/20090240995.pdf [firstpage_image] =>[orig_patent_app_number] => 12051744 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/051744
Method and apparatus for improving random pattern testing of logic structures Mar 18, 2008 Issued
Array ( [id] => 8011017 [patent_doc_number] => 08086926 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-12-27 [patent_title] => 'Failure diagnostic apparatus, failure diagnostic system, and failure diagnostic method' [patent_app_type] => utility [patent_app_number] => 12/051412 [patent_app_country] => US [patent_app_date] => 2008-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 5608 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/086/08086926.pdf [firstpage_image] =>[orig_patent_app_number] => 12051412 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/051412
Failure diagnostic apparatus, failure diagnostic system, and failure diagnostic method Mar 18, 2008 Issued
Array ( [id] => 4592860 [patent_doc_number] => 07853836 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-14 [patent_title] => 'Semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 12/047753 [patent_app_country] => US [patent_app_date] => 2008-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 3946 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/853/07853836.pdf [firstpage_image] =>[orig_patent_app_number] => 12047753 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/047753
Semiconductor integrated circuit Mar 12, 2008 Issued
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