
Shengjun Wang
Examiner (ID: 18947, Phone: (571)272-0632 , Office: P/1627 )
| Most Active Art Unit | 1627 |
| Art Unit(s) | 1627, 1617 |
| Total Applications | 2559 |
| Issued Applications | 1079 |
| Pending Applications | 238 |
| Abandoned Applications | 1248 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4885363
[patent_doc_number] => 20080259695
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-10-23
[patent_title] => 'Semiconductor Memory Devices Having a Demultiplexer and Related Methods of Testing Such Semiconductor Memory Devices'
[patent_app_type] => utility
[patent_app_number] => 12/044094
[patent_app_country] => US
[patent_app_date] => 2008-03-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 5997
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0259/20080259695.pdf
[firstpage_image] =>[orig_patent_app_number] => 12044094
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/044094 | Semiconductor Memory Devices Having a Demultiplexer and Related Methods of Testing Such Semiconductor Memory Devices | Mar 6, 2008 | Abandoned |
Array
(
[id] => 4741892
[patent_doc_number] => 20080235545
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-09-25
[patent_title] => 'Re-using production test scan paths for system test of an integrated circuit'
[patent_app_type] => utility
[patent_app_number] => 12/074722
[patent_app_country] => US
[patent_app_date] => 2008-03-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4378
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0235/20080235545.pdf
[firstpage_image] =>[orig_patent_app_number] => 12074722
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/074722 | Re-using production test scan paths for system test of an integrated circuit | Mar 4, 2008 | Abandoned |
Array
(
[id] => 4614278
[patent_doc_number] => 07996738
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-08-09
[patent_title] => 'Semiconductor chip with a plurality of scannable storage elements and a method for scanning storage elements on a semiconductor chip'
[patent_app_type] => utility
[patent_app_number] => 12/042944
[patent_app_country] => US
[patent_app_date] => 2008-03-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 3659
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 282
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/996/07996738.pdf
[firstpage_image] =>[orig_patent_app_number] => 12042944
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/042944 | Semiconductor chip with a plurality of scannable storage elements and a method for scanning storage elements on a semiconductor chip | Mar 4, 2008 | Issued |
Array
(
[id] => 6272930
[patent_doc_number] => 20100299575
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-11-25
[patent_title] => 'METHOD AND SYSTEM FOR DETECTION AND CORRECTION OF PHASED-BURST ERRORS, ERASURES, SYMBOL ERRORS, AND BIT ERRORS IN A RECEIVED SYMBOL STRING'
[patent_app_type] => utility
[patent_app_number] => 12/864233
[patent_app_country] => US
[patent_app_date] => 2008-03-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 26
[patent_no_of_words] => 12867
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0299/20100299575.pdf
[firstpage_image] =>[orig_patent_app_number] => 12864233
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/864233 | METHOD AND SYSTEM FOR DETECTION AND CORRECTION OF PHASED-BURST ERRORS, ERASURES, SYMBOL ERRORS, AND BIT ERRORS IN A RECEIVED SYMBOL STRING | Mar 2, 2008 | Abandoned |
Array
(
[id] => 4678312
[patent_doc_number] => 20080215943
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-09-04
[patent_title] => 'Generating test sets for diagnosing scan chain failures'
[patent_app_type] => utility
[patent_app_number] => 12/074162
[patent_app_country] => US
[patent_app_date] => 2008-02-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 16718
[patent_no_of_claims] => 42
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0215/20080215943.pdf
[firstpage_image] =>[orig_patent_app_number] => 12074162
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/074162 | Generating test sets for diagnosing scan chain failures | Feb 28, 2008 | Issued |
Array
(
[id] => 4678312
[patent_doc_number] => 20080215943
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-09-04
[patent_title] => 'Generating test sets for diagnosing scan chain failures'
[patent_app_type] => utility
[patent_app_number] => 12/074162
[patent_app_country] => US
[patent_app_date] => 2008-02-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 16718
[patent_no_of_claims] => 42
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0215/20080215943.pdf
[firstpage_image] =>[orig_patent_app_number] => 12074162
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/074162 | Generating test sets for diagnosing scan chain failures | Feb 28, 2008 | Issued |
Array
(
[id] => 4678312
[patent_doc_number] => 20080215943
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-09-04
[patent_title] => 'Generating test sets for diagnosing scan chain failures'
[patent_app_type] => utility
[patent_app_number] => 12/074162
[patent_app_country] => US
[patent_app_date] => 2008-02-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 16718
[patent_no_of_claims] => 42
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0215/20080215943.pdf
[firstpage_image] =>[orig_patent_app_number] => 12074162
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/074162 | Generating test sets for diagnosing scan chain failures | Feb 28, 2008 | Issued |
Array
(
[id] => 4678312
[patent_doc_number] => 20080215943
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-09-04
[patent_title] => 'Generating test sets for diagnosing scan chain failures'
[patent_app_type] => utility
[patent_app_number] => 12/074162
[patent_app_country] => US
[patent_app_date] => 2008-02-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 16718
[patent_no_of_claims] => 42
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0215/20080215943.pdf
[firstpage_image] =>[orig_patent_app_number] => 12074162
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/074162 | Generating test sets for diagnosing scan chain failures | Feb 28, 2008 | Issued |
Array
(
[id] => 5540891
[patent_doc_number] => 20090222696
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-09-03
[patent_title] => 'SYSTEM AND METHOD FOR DETECTING NON-REPRODUCIBLE PSEUDO-RANDOM TEST CASES'
[patent_app_type] => utility
[patent_app_number] => 12/039122
[patent_app_country] => US
[patent_app_date] => 2008-02-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4453
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0222/20090222696.pdf
[firstpage_image] =>[orig_patent_app_number] => 12039122
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/039122 | System and method for detecting non-reproducible pseudo-random test cases | Feb 27, 2008 | Issued |
Array
(
[id] => 97441
[patent_doc_number] => 07739567
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-06-15
[patent_title] => 'Utilizing serializer-deserializer transmit and receive pads for parallel scan test data'
[patent_app_type] => utility
[patent_app_number] => 12/037157
[patent_app_country] => US
[patent_app_date] => 2008-02-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 3362
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 221
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/739/07739567.pdf
[firstpage_image] =>[orig_patent_app_number] => 12037157
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/037157 | Utilizing serializer-deserializer transmit and receive pads for parallel scan test data | Feb 25, 2008 | Issued |
Array
(
[id] => 4488700
[patent_doc_number] => 07908534
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-03-15
[patent_title] => 'Diagnosable general purpose test registers scan chain design'
[patent_app_type] => utility
[patent_app_number] => 12/036320
[patent_app_country] => US
[patent_app_date] => 2008-02-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4674
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/908/07908534.pdf
[firstpage_image] =>[orig_patent_app_number] => 12036320
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/036320 | Diagnosable general purpose test registers scan chain design | Feb 24, 2008 | Issued |
Array
(
[id] => 4573661
[patent_doc_number] => 07962832
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-06-14
[patent_title] => 'Method for detecting memory error'
[patent_app_type] => utility
[patent_app_number] => 12/036550
[patent_app_country] => US
[patent_app_date] => 2008-02-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 4239
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 254
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/962/07962832.pdf
[firstpage_image] =>[orig_patent_app_number] => 12036550
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/036550 | Method for detecting memory error | Feb 24, 2008 | Issued |
Array
(
[id] => 4447596
[patent_doc_number] => 07930608
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-04-19
[patent_title] => 'Circuit for controlling voltage fluctuation in integrated circuit'
[patent_app_type] => utility
[patent_app_number] => 12/035536
[patent_app_country] => US
[patent_app_date] => 2008-02-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 9
[patent_no_of_words] => 4912
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 228
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/930/07930608.pdf
[firstpage_image] =>[orig_patent_app_number] => 12035536
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/035536 | Circuit for controlling voltage fluctuation in integrated circuit | Feb 21, 2008 | Issued |
Array
(
[id] => 4951046
[patent_doc_number] => 20080307172
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-12-11
[patent_title] => 'SYSTEM AND METHOD FOR REPRODUCING MEMORY ERROR'
[patent_app_type] => utility
[patent_app_number] => 12/033231
[patent_app_country] => US
[patent_app_date] => 2008-02-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3411
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0307/20080307172.pdf
[firstpage_image] =>[orig_patent_app_number] => 12033231
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/033231 | System and method for reproducing memory error | Feb 18, 2008 | Issued |
Array
(
[id] => 206569
[patent_doc_number] => 07634701
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-12-15
[patent_title] => 'Method and system for protecting processors from unauthorized debug access'
[patent_app_type] => utility
[patent_app_number] => 12/033864
[patent_app_country] => US
[patent_app_date] => 2008-02-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 6115
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/634/07634701.pdf
[firstpage_image] =>[orig_patent_app_number] => 12033864
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/033864 | Method and system for protecting processors from unauthorized debug access | Feb 18, 2008 | Issued |
Array
(
[id] => 5393253
[patent_doc_number] => 20090210566
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-08-20
[patent_title] => 'MULTI-CHIP DIGITAL SYSTEM SIGNAL IDENTIFICATION APPARATUS'
[patent_app_type] => utility
[patent_app_number] => 12/032990
[patent_app_country] => US
[patent_app_date] => 2008-02-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 5107
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0210/20090210566.pdf
[firstpage_image] =>[orig_patent_app_number] => 12032990
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/032990 | Multi-chip digital system having a plurality of controllers with self-identifying signal | Feb 17, 2008 | Issued |
Array
(
[id] => 66570
[patent_doc_number] => 07765448
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-07-27
[patent_title] => 'Clock signal distributing circuit, information processing device and clock signal distributing method'
[patent_app_type] => utility
[patent_app_number] => 12/031116
[patent_app_country] => US
[patent_app_date] => 2008-02-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 6414
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/765/07765448.pdf
[firstpage_image] =>[orig_patent_app_number] => 12031116
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/031116 | Clock signal distributing circuit, information processing device and clock signal distributing method | Feb 13, 2008 | Issued |
Array
(
[id] => 4678305
[patent_doc_number] => 20080215936
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-09-04
[patent_title] => 'Non-chronological AV-stream recording'
[patent_app_type] => utility
[patent_app_number] => 12/069840
[patent_app_country] => US
[patent_app_date] => 2008-02-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2489
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0215/20080215936.pdf
[firstpage_image] =>[orig_patent_app_number] => 12069840
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/069840 | Non-chronological AV-stream recording | Feb 12, 2008 | Abandoned |
Array
(
[id] => 4815268
[patent_doc_number] => 20080195899
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-08-14
[patent_title] => 'Apparatus and method for deciding adaptive target packet error rate in wireless communication system'
[patent_app_type] => utility
[patent_app_number] => 12/069675
[patent_app_country] => US
[patent_app_date] => 2008-02-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3551
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0195/20080195899.pdf
[firstpage_image] =>[orig_patent_app_number] => 12069675
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/069675 | Apparatus and method for deciding adaptive target packet error rate in wireless communication system | Feb 11, 2008 | Issued |
Array
(
[id] => 5574241
[patent_doc_number] => 20090141602
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-06-04
[patent_title] => 'RECORDING MEDIUM STRUCTURE CAPABLE OF DISPLAYING DEFECT RATE'
[patent_app_type] => utility
[patent_app_number] => 12/024118
[patent_app_country] => US
[patent_app_date] => 2008-02-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 5931
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0141/20090141602.pdf
[firstpage_image] =>[orig_patent_app_number] => 12024118
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/024118 | Recording medium structure capable of displaying defect rate | Jan 31, 2008 | Issued |