
Sherrie Y. Hsia
Examiner (ID: 4542, Phone: (571)272-7347 , Office: P/2422 )
| Most Active Art Unit | 2422 |
| Art Unit(s) | 2614, 2505, 2602, 2714, 2422, 2622, 2899 |
| Total Applications | 2705 |
| Issued Applications | 2465 |
| Pending Applications | 94 |
| Abandoned Applications | 164 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7333220
[patent_doc_number] => 20040255090
[patent_country] => US
[patent_kind] => A1
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[patent_title] => 'Tracking cells for a memory system'
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[patent_app_date] => 2003-06-13
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Array
(
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[patent_title] => 'Data storage'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/461753 | Data storage | Jun 12, 2003 | Issued |
| 10/461604 | Computerized system for facilitating transactions between parties on the internet using e-mail | Jun 11, 2003 | Abandoned |
Array
(
[id] => 6665370
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[patent_title] => 'Mechanism for synchronizing multiple skewed source-synchronous data channels with automatic initialization feature'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/441451 | Mechanism for synchronizing multiple skewed source-synchronous data channels with automatic initialization feature | May 19, 2003 | Issued |
Array
(
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[patent_issue_date] => 2005-11-22
[patent_title] => 'Method and system for altering a sequence number assignment pattern while preserving integrity and high concurrency in a multi-system shared disk environment'
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Array
(
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[patent_title] => 'Methods and systems of cache memory management and snapshot operations'
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Array
(
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/424142 | Apparatus and method for tandem operation in a storage network | Apr 24, 2003 | Issued |
Array
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[patent_title] => 'System and method for facilitating communication across an asynchronous clock boundary'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/423993 | System and method for facilitating communication across an asynchronous clock boundary | Apr 24, 2003 | Issued |
Array
(
[id] => 789390
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[patent_title] => 'Microprocessor, apparatus and method for selectively associating store buffer cache line status with response buffer cache line status'
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Array
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[patent_title] => 'Scalable directory based cache coherence protocol'
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Array
(
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Array
(
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Array
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Array
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Array
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Array
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Array
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