Search

Sherrod L. Keaton

Examiner (ID: 16179, Phone: (571)270-1697 , Office: P/2142 )

Most Active Art Unit
2142
Art Unit(s)
2178, 2174, 2175, 2148, 2142, 2173
Total Applications
634
Issued Applications
300
Pending Applications
61
Abandoned Applications
282

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6876695 [patent_doc_number] => 20010006848 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-07-05 [patent_title] => 'Methylated oxide-type dielectric as a replacement for SiO2 hardmasks used in polymeric low K, dual damascene interconnect integration' [patent_app_type] => new-utility [patent_app_number] => 09/738589 [patent_app_country] => US [patent_app_date] => 2000-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1301 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20010006848.pdf [firstpage_image] =>[orig_patent_app_number] => 09738589 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/738589
Methylated oxide-type dielectric as a replacement for SiO2 hardmasks used in polymeric low k, dual damascene interconnect integration Dec 14, 2000 Issued
Array ( [id] => 7645658 [patent_doc_number] => 06472311 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-29 [patent_title] => 'Method for manufacturing semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/719688 [patent_app_country] => US [patent_app_date] => 2000-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 14 [patent_no_of_words] => 3023 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 12 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/472/06472311.pdf [firstpage_image] =>[orig_patent_app_number] => 09719688 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/719688
Method for manufacturing semiconductor device Dec 14, 2000 Issued
Array ( [id] => 1361783 [patent_doc_number] => 06569746 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-05-27 [patent_title] => 'Methods of forming integrated circuit capacitors having electrodes therein that comprise conductive plugs' [patent_app_type] => B2 [patent_app_number] => 09/733716 [patent_app_country] => US [patent_app_date] => 2000-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3818 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/569/06569746.pdf [firstpage_image] =>[orig_patent_app_number] => 09733716 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/733716
Methods of forming integrated circuit capacitors having electrodes therein that comprise conductive plugs Dec 7, 2000 Issued
Array ( [id] => 1328303 [patent_doc_number] => 06603199 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-08-05 [patent_title] => 'Integrated circuit package having die with staggered bond pads and die pad assignment methodology for assembly of staggered die in single-tier ebga packages' [patent_app_type] => B1 [patent_app_number] => 09/724739 [patent_app_country] => US [patent_app_date] => 2000-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 5814 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/603/06603199.pdf [firstpage_image] =>[orig_patent_app_number] => 09724739 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/724739
Integrated circuit package having die with staggered bond pads and die pad assignment methodology for assembly of staggered die in single-tier ebga packages Nov 27, 2000 Issued
Array ( [id] => 1146248 [patent_doc_number] => 06773977 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-10 [patent_title] => 'Method of forming a diode for integration with a semiconductor device and method of forming a transistor device having an integrated diode' [patent_app_type] => B1 [patent_app_number] => 09/715748 [patent_app_country] => US [patent_app_date] => 2000-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 2440 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/773/06773977.pdf [firstpage_image] =>[orig_patent_app_number] => 09715748 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/715748
Method of forming a diode for integration with a semiconductor device and method of forming a transistor device having an integrated diode Nov 16, 2000 Issued
Array ( [id] => 1594285 [patent_doc_number] => 06383848 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-07 [patent_title] => 'Method of isolating a SRAM cell' [patent_app_type] => B1 [patent_app_number] => 09/716108 [patent_app_country] => US [patent_app_date] => 2000-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4209 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/383/06383848.pdf [firstpage_image] =>[orig_patent_app_number] => 09716108 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/716108
Method of isolating a SRAM cell Nov 15, 2000 Issued
Array ( [id] => 1288591 [patent_doc_number] => 06639285 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-28 [patent_title] => 'Method for fabricating a semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/713106 [patent_app_country] => US [patent_app_date] => 2000-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3256 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/639/06639285.pdf [firstpage_image] =>[orig_patent_app_number] => 09713106 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/713106
Method for fabricating a semiconductor device Nov 14, 2000 Issued
Array ( [id] => 1462695 [patent_doc_number] => 06350708 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-26 [patent_title] => 'Silicon nitride deposition method' [patent_app_type] => B1 [patent_app_number] => 09/704140 [patent_app_country] => US [patent_app_date] => 2000-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 6740 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/350/06350708.pdf [firstpage_image] =>[orig_patent_app_number] => 09704140 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/704140
Silicon nitride deposition method Oct 31, 2000 Issued
Array ( [id] => 1559894 [patent_doc_number] => 06436827 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-20 [patent_title] => 'Fabrication method of a semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/704383 [patent_app_country] => US [patent_app_date] => 2000-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 6136 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 29 [patent_words_short_claim] => 18 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/436/06436827.pdf [firstpage_image] =>[orig_patent_app_number] => 09704383 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/704383
Fabrication method of a semiconductor device Oct 30, 2000 Issued
Array ( [id] => 1085660 [patent_doc_number] => 06831005 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-12-14 [patent_title] => 'Electron beam process during damascene processing' [patent_app_type] => B1 [patent_app_number] => 09/690649 [patent_app_country] => US [patent_app_date] => 2000-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 32 [patent_no_of_words] => 9896 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/831/06831005.pdf [firstpage_image] =>[orig_patent_app_number] => 09690649 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/690649
Electron beam process during damascene processing Oct 16, 2000 Issued
Array ( [id] => 1561006 [patent_doc_number] => 06362014 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-26 [patent_title] => 'Bonding apparatus' [patent_app_type] => B1 [patent_app_number] => 09/687842 [patent_app_country] => US [patent_app_date] => 2000-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2558 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/362/06362014.pdf [firstpage_image] =>[orig_patent_app_number] => 09687842 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/687842
Bonding apparatus Oct 12, 2000 Issued
Array ( [id] => 1503618 [patent_doc_number] => 06465334 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-15 [patent_title] => 'Enhanced electroless deposition of dielectric precursor materials for use in in-laid gate MOS transistors' [patent_app_type] => B1 [patent_app_number] => 09/679369 [patent_app_country] => US [patent_app_date] => 2000-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 7075 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/465/06465334.pdf [firstpage_image] =>[orig_patent_app_number] => 09679369 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/679369
Enhanced electroless deposition of dielectric precursor materials for use in in-laid gate MOS transistors Oct 4, 2000 Issued
Array ( [id] => 1433324 [patent_doc_number] => 06340614 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-22 [patent_title] => 'Method of forming a DRAM cell' [patent_app_type] => B1 [patent_app_number] => 09/678639 [patent_app_country] => US [patent_app_date] => 2000-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2650 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/340/06340614.pdf [firstpage_image] =>[orig_patent_app_number] => 09678639 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/678639
Method of forming a DRAM cell Oct 2, 2000 Issued
Array ( [id] => 1441034 [patent_doc_number] => 06335257 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-01 [patent_title] => 'Method of making pillar-type structure on semiconductor substrate' [patent_app_type] => B1 [patent_app_number] => 09/672999 [patent_app_country] => US [patent_app_date] => 2000-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 1068 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 337 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/335/06335257.pdf [firstpage_image] =>[orig_patent_app_number] => 09672999 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/672999
Method of making pillar-type structure on semiconductor substrate Sep 28, 2000 Issued
Array ( [id] => 1459379 [patent_doc_number] => 06391720 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Process flow for a performance enhanced MOSFET with self-aligned, recessed channel' [patent_app_type] => B1 [patent_app_number] => 09/671509 [patent_app_country] => US [patent_app_date] => 2000-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 24 [patent_no_of_words] => 2919 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 359 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/391/06391720.pdf [firstpage_image] =>[orig_patent_app_number] => 09671509 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/671509
Process flow for a performance enhanced MOSFET with self-aligned, recessed channel Sep 26, 2000 Issued
Array ( [id] => 1559804 [patent_doc_number] => 06436799 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-20 [patent_title] => 'Process for annealing semiconductors and/or integrated circuits' [patent_app_type] => B1 [patent_app_number] => 09/670089 [patent_app_country] => US [patent_app_date] => 2000-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 2208 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/436/06436799.pdf [firstpage_image] =>[orig_patent_app_number] => 09670089 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/670089
Process for annealing semiconductors and/or integrated circuits Sep 25, 2000 Issued
Array ( [id] => 1169088 [patent_doc_number] => 06753272 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-22 [patent_title] => 'High-performance energy transfer method for thermal processing applications' [patent_app_type] => B1 [patent_app_number] => 09/669039 [patent_app_country] => US [patent_app_date] => 2000-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 6291 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/753/06753272.pdf [firstpage_image] =>[orig_patent_app_number] => 09669039 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/669039
High-performance energy transfer method for thermal processing applications Sep 24, 2000 Issued
Array ( [id] => 1581225 [patent_doc_number] => 06423633 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-23 [patent_title] => 'Method for manufacturing diffusion barrier layer' [patent_app_type] => B1 [patent_app_number] => 09/670204 [patent_app_country] => US [patent_app_date] => 2000-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1918 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/423/06423633.pdf [firstpage_image] =>[orig_patent_app_number] => 09670204 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/670204
Method for manufacturing diffusion barrier layer Sep 24, 2000 Issued
Array ( [id] => 1071892 [patent_doc_number] => 06841476 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-01-11 [patent_title] => 'Electroless plating method' [patent_app_type] => utility [patent_app_number] => 10/088489 [patent_app_country] => US [patent_app_date] => 2000-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 7771 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/841/06841476.pdf [firstpage_image] =>[orig_patent_app_number] => 10088489 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/088489
Electroless plating method Sep 21, 2000 Issued
Array ( [id] => 7640343 [patent_doc_number] => 06395571 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-28 [patent_title] => 'Method for fabricating polysilicon TFT' [patent_app_type] => B1 [patent_app_number] => 09/665119 [patent_app_country] => US [patent_app_date] => 2000-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 24 [patent_no_of_words] => 3177 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 11 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/395/06395571.pdf [firstpage_image] =>[orig_patent_app_number] => 09665119 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/665119
Method for fabricating polysilicon TFT Sep 19, 2000 Issued
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