
Sherrod L. Keaton
Examiner (ID: 16179, Phone: (571)270-1697 , Office: P/2142 )
| Most Active Art Unit | 2142 |
| Art Unit(s) | 2178, 2174, 2175, 2148, 2142, 2173 |
| Total Applications | 634 |
| Issued Applications | 300 |
| Pending Applications | 61 |
| Abandoned Applications | 282 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 6876695
[patent_doc_number] => 20010006848
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-07-05
[patent_title] => 'Methylated oxide-type dielectric as a replacement for SiO2 hardmasks used in polymeric low K, dual damascene interconnect integration'
[patent_app_type] => new-utility
[patent_app_number] => 09/738589
[patent_app_country] => US
[patent_app_date] => 2000-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 1301
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[patent_words_short_claim] => 31
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0006/20010006848.pdf
[firstpage_image] =>[orig_patent_app_number] => 09738589
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/738589 | Methylated oxide-type dielectric as a replacement for SiO2 hardmasks used in polymeric low k, dual damascene interconnect integration | Dec 14, 2000 | Issued |
Array
(
[id] => 7645658
[patent_doc_number] => 06472311
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-10-29
[patent_title] => 'Method for manufacturing semiconductor device'
[patent_app_type] => B1
[patent_app_number] => 09/719688
[patent_app_country] => US
[patent_app_date] => 2000-12-15
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/719688 | Method for manufacturing semiconductor device | Dec 14, 2000 | Issued |
Array
(
[id] => 1361783
[patent_doc_number] => 06569746
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[patent_kind] => B2
[patent_issue_date] => 2003-05-27
[patent_title] => 'Methods of forming integrated circuit capacitors having electrodes therein that comprise conductive plugs'
[patent_app_type] => B2
[patent_app_number] => 09/733716
[patent_app_country] => US
[patent_app_date] => 2000-12-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[firstpage_image] =>[orig_patent_app_number] => 09733716
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/733716 | Methods of forming integrated circuit capacitors having electrodes therein that comprise conductive plugs | Dec 7, 2000 | Issued |
Array
(
[id] => 1328303
[patent_doc_number] => 06603199
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-08-05
[patent_title] => 'Integrated circuit package having die with staggered bond pads and die pad assignment methodology for assembly of staggered die in single-tier ebga packages'
[patent_app_type] => B1
[patent_app_number] => 09/724739
[patent_app_country] => US
[patent_app_date] => 2000-11-28
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 09724739
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/724739 | Integrated circuit package having die with staggered bond pads and die pad assignment methodology for assembly of staggered die in single-tier ebga packages | Nov 27, 2000 | Issued |
Array
(
[id] => 1146248
[patent_doc_number] => 06773977
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[patent_kind] => B1
[patent_issue_date] => 2004-08-10
[patent_title] => 'Method of forming a diode for integration with a semiconductor device and method of forming a transistor device having an integrated diode'
[patent_app_type] => B1
[patent_app_number] => 09/715748
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/715748 | Method of forming a diode for integration with a semiconductor device and method of forming a transistor device having an integrated diode | Nov 16, 2000 | Issued |
Array
(
[id] => 1594285
[patent_doc_number] => 06383848
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-05-07
[patent_title] => 'Method of isolating a SRAM cell'
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[patent_app_number] => 09/716108
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[firstpage_image] =>[orig_patent_app_number] => 09716108
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/716108 | Method of isolating a SRAM cell | Nov 15, 2000 | Issued |
Array
(
[id] => 1288591
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[patent_kind] => B1
[patent_issue_date] => 2003-10-28
[patent_title] => 'Method for fabricating a semiconductor device'
[patent_app_type] => B1
[patent_app_number] => 09/713106
[patent_app_country] => US
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[pdf_file] => patents/06/639/06639285.pdf
[firstpage_image] =>[orig_patent_app_number] => 09713106
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/713106 | Method for fabricating a semiconductor device | Nov 14, 2000 | Issued |
Array
(
[id] => 1462695
[patent_doc_number] => 06350708
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-02-26
[patent_title] => 'Silicon nitride deposition method'
[patent_app_type] => B1
[patent_app_number] => 09/704140
[patent_app_country] => US
[patent_app_date] => 2000-11-01
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/350/06350708.pdf
[firstpage_image] =>[orig_patent_app_number] => 09704140
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/704140 | Silicon nitride deposition method | Oct 31, 2000 | Issued |
Array
(
[id] => 1559894
[patent_doc_number] => 06436827
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[patent_issue_date] => 2002-08-20
[patent_title] => 'Fabrication method of a semiconductor device'
[patent_app_type] => B1
[patent_app_number] => 09/704383
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[firstpage_image] =>[orig_patent_app_number] => 09704383
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/704383 | Fabrication method of a semiconductor device | Oct 30, 2000 | Issued |
Array
(
[id] => 1085660
[patent_doc_number] => 06831005
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[patent_kind] => B1
[patent_issue_date] => 2004-12-14
[patent_title] => 'Electron beam process during damascene processing'
[patent_app_type] => B1
[patent_app_number] => 09/690649
[patent_app_country] => US
[patent_app_date] => 2000-10-17
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/690649 | Electron beam process during damascene processing | Oct 16, 2000 | Issued |
Array
(
[id] => 1561006
[patent_doc_number] => 06362014
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[patent_issue_date] => 2002-03-26
[patent_title] => 'Bonding apparatus'
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[patent_app_number] => 09/687842
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/687842 | Bonding apparatus | Oct 12, 2000 | Issued |
Array
(
[id] => 1503618
[patent_doc_number] => 06465334
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[patent_issue_date] => 2002-10-15
[patent_title] => 'Enhanced electroless deposition of dielectric precursor materials for use in in-laid gate MOS transistors'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/679369 | Enhanced electroless deposition of dielectric precursor materials for use in in-laid gate MOS transistors | Oct 4, 2000 | Issued |
Array
(
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[patent_title] => 'Method of forming a DRAM cell'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/678639 | Method of forming a DRAM cell | Oct 2, 2000 | Issued |
Array
(
[id] => 1441034
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[patent_title] => 'Method of making pillar-type structure on semiconductor substrate'
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Array
(
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Array
(
[id] => 1559804
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[patent_title] => 'Process for annealing semiconductors and/or integrated circuits'
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Array
(
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Array
(
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/088489 | Electroless plating method | Sep 21, 2000 | Issued |
Array
(
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[firstpage_image] =>[orig_patent_app_number] => 09665119
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/665119 | Method for fabricating polysilicon TFT | Sep 19, 2000 | Issued |