Search

Shrive Beck

Examiner (ID: 12631)

Most Active Art Unit
1502
Art Unit(s)
1502, 3203, 1762, 1112, 2899, 1309
Total Applications
800
Issued Applications
693
Pending Applications
2
Abandoned Applications
105

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1229151 [patent_doc_number] => 06701408 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-02 [patent_title] => 'Data processing device with a memory location in which data is stored according to a WOM code' [patent_app_type] => B2 [patent_app_number] => 10/014226 [patent_app_country] => US [patent_app_date] => 2001-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 7058 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/701/06701408.pdf [firstpage_image] =>[orig_patent_app_number] => 10014226 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/014226
Data processing device with a memory location in which data is stored according to a WOM code Dec 10, 2001 Issued
Array ( [id] => 1258424 [patent_doc_number] => 06671790 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-12-30 [patent_title] => 'Optimizing reader to writer offset compensation for a disc drive' [patent_app_type] => B2 [patent_app_number] => 09/971348 [patent_app_country] => US [patent_app_date] => 2001-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 8236 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/671/06671790.pdf [firstpage_image] =>[orig_patent_app_number] => 09971348 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/971348
Optimizing reader to writer offset compensation for a disc drive Oct 3, 2001 Issued
Array ( [id] => 6632232 [patent_doc_number] => 20020066000 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-30 [patent_title] => 'Transporting data transmission units of different sizes using segments of fixed sizes' [patent_app_type] => new [patent_app_number] => 09/969806 [patent_app_country] => US [patent_app_date] => 2001-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6500 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20020066000.pdf [firstpage_image] =>[orig_patent_app_number] => 09969806 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/969806
Transporting data transmission units of different sizes using segments of fixed sizes Oct 3, 2001 Issued
Array ( [id] => 6134004 [patent_doc_number] => 20020078311 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-20 [patent_title] => 'Multi-port memory based on DRAM core' [patent_app_type] => new [patent_app_number] => 09/968516 [patent_app_country] => US [patent_app_date] => 2001-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 140 [patent_figures_cnt] => 140 [patent_no_of_words] => 48101 [patent_no_of_claims] => 91 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0078/20020078311.pdf [firstpage_image] =>[orig_patent_app_number] => 09968516 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/968516
Multi-port memory based on DRAM core Oct 1, 2001 Abandoned
Array ( [id] => 7962257 [patent_doc_number] => 06681301 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-20 [patent_title] => 'System for controlling multiple memory types' [patent_app_type] => B1 [patent_app_number] => 09/969303 [patent_app_country] => US [patent_app_date] => 2001-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 7657 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/681/06681301.pdf [firstpage_image] =>[orig_patent_app_number] => 09969303 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/969303
System for controlling multiple memory types Oct 1, 2001 Issued
Array ( [id] => 1260449 [patent_doc_number] => 06668306 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-12-23 [patent_title] => 'Non-vital loads' [patent_app_type] => B2 [patent_app_number] => 09/881314 [patent_app_country] => US [patent_app_date] => 2001-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2590 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/668/06668306.pdf [firstpage_image] =>[orig_patent_app_number] => 09881314 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/881314
Non-vital loads Jun 11, 2001 Issued
Array ( [id] => 6335916 [patent_doc_number] => 20020199077 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-26 [patent_title] => 'Method to partition a data storage and retrieval system into one or more logical libraries' [patent_app_type] => new [patent_app_number] => 09/878469 [patent_app_country] => US [patent_app_date] => 2001-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 8510 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0199/20020199077.pdf [firstpage_image] =>[orig_patent_app_number] => 09878469 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/878469
Method to partition a data storage and retrieval system into one or more logical libraries Jun 10, 2001 Issued
Array ( [id] => 1314415 [patent_doc_number] => 06622217 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-09-16 [patent_title] => 'Cache coherence protocol engine system and method for processing memory transaction in distinct address subsets during interleaved time periods in a multiprocessor system' [patent_app_type] => B2 [patent_app_number] => 09/878983 [patent_app_country] => US [patent_app_date] => 2001-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 30 [patent_no_of_words] => 20336 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/622/06622217.pdf [firstpage_image] =>[orig_patent_app_number] => 09878983 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/878983
Cache coherence protocol engine system and method for processing memory transaction in distinct address subsets during interleaved time periods in a multiprocessor system Jun 10, 2001 Issued
Array ( [id] => 1200990 [patent_doc_number] => 06728848 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-04-27 [patent_title] => 'Method and system for backing up storage system data' [patent_app_type] => B2 [patent_app_number] => 09/879663 [patent_app_country] => US [patent_app_date] => 2001-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 7116 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/728/06728848.pdf [firstpage_image] =>[orig_patent_app_number] => 09879663 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/879663
Method and system for backing up storage system data Jun 10, 2001 Issued
Array ( [id] => 6181369 [patent_doc_number] => 20020156990 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-24 [patent_title] => 'Modulus address generator and method for determining a modulus address' [patent_app_type] => new [patent_app_number] => 09/878879 [patent_app_country] => US [patent_app_date] => 2001-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3451 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 343 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0156/20020156990.pdf [firstpage_image] =>[orig_patent_app_number] => 09878879 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/878879
Modulus address generator and method for determining a modulus address Jun 10, 2001 Issued
Array ( [id] => 5803502 [patent_doc_number] => 20020010840 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-24 [patent_title] => 'Multiprocessor cache coherence system and method in which processor nodes and input/output nodes are equal participants' [patent_app_type] => new [patent_app_number] => 09/878984 [patent_app_country] => US [patent_app_date] => 2001-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 19995 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0010/20020010840.pdf [firstpage_image] =>[orig_patent_app_number] => 09878984 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/878984
Multiprocessor cache coherence system and method in which processor nodes and input/output nodes are equal participants Jun 10, 2001 Issued
Array ( [id] => 1234274 [patent_doc_number] => 06697919 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-02-24 [patent_title] => 'System and method for limited fanout daisy chaining of cache invalidation requests in a shared-memory multiprocessor system' [patent_app_type] => B2 [patent_app_number] => 09/878985 [patent_app_country] => US [patent_app_date] => 2001-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 30 [patent_no_of_words] => 20279 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 399 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/697/06697919.pdf [firstpage_image] =>[orig_patent_app_number] => 09878985 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/878985
System and method for limited fanout daisy chaining of cache invalidation requests in a shared-memory multiprocessor system Jun 10, 2001 Issued
Array ( [id] => 5952992 [patent_doc_number] => 20020007443 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-17 [patent_title] => 'Scalable multiprocessor system and cache coherence method' [patent_app_type] => new [patent_app_number] => 09/878982 [patent_app_country] => US [patent_app_date] => 2001-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 20497 [patent_no_of_claims] => 56 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0007/20020007443.pdf [firstpage_image] =>[orig_patent_app_number] => 09878982 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/878982
Scalable multiprocessor system and cache coherence method Jun 10, 2001 Issued
Array ( [id] => 5803606 [patent_doc_number] => 20020010891 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-24 [patent_title] => 'Redundant memory access system' [patent_app_type] => new [patent_app_number] => 09/795419 [patent_app_country] => US [patent_app_date] => 2001-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5723 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0010/20020010891.pdf [firstpage_image] =>[orig_patent_app_number] => 09795419 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/795419
Redundant memory access system Feb 27, 2001 Abandoned
Array ( [id] => 7631550 [patent_doc_number] => 06665787 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-12-16 [patent_title] => 'Very high speed page operations in indirect accessed memory systems' [patent_app_type] => B2 [patent_app_number] => 09/795414 [patent_app_country] => US [patent_app_date] => 2001-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 7575 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/665/06665787.pdf [firstpage_image] =>[orig_patent_app_number] => 09795414 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/795414
Very high speed page operations in indirect accessed memory systems Feb 27, 2001 Issued
Array ( [id] => 1314509 [patent_doc_number] => 06622229 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-09-16 [patent_title] => 'Virtual memory structure' [patent_app_type] => B2 [patent_app_number] => 09/796188 [patent_app_country] => US [patent_app_date] => 2001-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1497 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/622/06622229.pdf [firstpage_image] =>[orig_patent_app_number] => 09796188 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/796188
Virtual memory structure Feb 27, 2001 Issued
Array ( [id] => 1381521 [patent_doc_number] => 06574706 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-06-03 [patent_title] => 'Managing unvirtualized data pages in real storage' [patent_app_type] => B2 [patent_app_number] => 09/795425 [patent_app_country] => US [patent_app_date] => 2001-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3580 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/574/06574706.pdf [firstpage_image] =>[orig_patent_app_number] => 09795425 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/795425
Managing unvirtualized data pages in real storage Feb 27, 2001 Issued
Array ( [id] => 6388915 [patent_doc_number] => 20020120821 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-29 [patent_title] => 'Excessive spin detection and avoidance for systems using a least recently used page replacement algorithm' [patent_app_type] => new [patent_app_number] => 09/795728 [patent_app_country] => US [patent_app_date] => 2001-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4059 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0120/20020120821.pdf [firstpage_image] =>[orig_patent_app_number] => 09795728 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/795728
Excessive spin detection and avoidance for systems using a least recently used page replacement algorithm Feb 27, 2001 Issued
Array ( [id] => 1234259 [patent_doc_number] => 06697914 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-24 [patent_title] => 'Switched node comprising a disk controller with integrated multi-port switching circuitry' [patent_app_type] => B1 [patent_app_number] => 09/660002 [patent_app_country] => US [patent_app_date] => 2000-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3212 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/697/06697914.pdf [firstpage_image] =>[orig_patent_app_number] => 09660002 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/660002
Switched node comprising a disk controller with integrated multi-port switching circuitry Sep 10, 2000 Issued
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