Sidney Li

Array ( [id] => 19466484 [patent_doc_number] => 20240320154 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => MULTI-LEVEL CACHE SECURITY [patent_app_type] => utility [patent_app_number] => 18/733125 [patent_app_country] => US [patent_app_date] => 2024-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18774 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18733125 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20513075 [patent_doc_number] => 20260037176 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-02-05 [patent_title] => DATA PROCESSING METHOD AND APPARATUS, SERVER, AND STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 19/139456 [patent_app_country] => US [patent_app_date] => 2024-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3565 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19139456 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20257908 [patent_doc_number] => 12430258 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-30 [patent_title] => Padding cached data with valid data for memory flush commands [patent_app_type] => utility [patent_app_number] => 18/672645 [patent_app_country] => US [patent_app_date] => 2024-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4031 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18672645 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20883613 [patent_doc_number] => 12699656 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-08-04 [patent_title] => Memory storage device and method [patent_app_type] => utility [patent_app_number] => 18/646226 [patent_app_country] => US [patent_app_date] => 2024-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18646226 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19588413 [patent_doc_number] => 20240385970 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-21 [patent_title] => METHODS, SYSTEMS, ARTICLES OF MANUFACTURE AND APPARATUS TO CONTROL ADDRESS SPACE ISOLATION IN A VIRTUAL MACHINE [patent_app_type] => utility [patent_app_number] => 18/625880 [patent_app_country] => US [patent_app_date] => 2024-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11726 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18625880 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19856979 [patent_doc_number] => 12259813 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-25 [patent_title] => Controller for controlling non-volatile semiconductor memory and method of controlling non-volatile semiconductor memory [patent_app_type] => utility [patent_app_number] => 18/624930 [patent_app_country] => US [patent_app_date] => 2024-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 48 [patent_no_of_words] => 37425 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18624930 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20537563 [patent_doc_number] => 12554640 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-17 [patent_title] => Apparatuses, systems, and methods for controlling cache allocations in a configurable combined private and shared cache in a processor-based system [patent_app_type] => utility [patent_app_number] => 18/623366 [patent_app_country] => US [patent_app_date] => 2024-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1088 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18623366 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20249887 [patent_doc_number] => 20250298756 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-25 [patent_title] => METHOD AND APPARATUS FOR SCALABLE EXCLUSIVE ACCESS MANAGEMENT IN MEMORY SYSTEMS [patent_app_type] => utility [patent_app_number] => 18/610080 [patent_app_country] => US [patent_app_date] => 2024-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14611 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18610080 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19660648 [patent_doc_number] => 20240427713 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-26 [patent_title] => STORAGE APPARATUS AND CONTROL METHOD FOR STORAGE APPARATUS [patent_app_type] => utility [patent_app_number] => 18/599738 [patent_app_country] => US [patent_app_date] => 2024-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7895 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 536 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18599738 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20434228 [patent_doc_number] => 12504915 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-23 [patent_title] => Performing memory access operations based on quad-level cell to single-level cell mapping table [patent_app_type] => utility [patent_app_number] => 18/433688 [patent_app_country] => US [patent_app_date] => 2024-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3950 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18433688 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20580031 [patent_doc_number] => 12572281 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-10 [patent_title] => Adaptive die selection for block family scan [patent_app_type] => utility [patent_app_number] => 18/403255 [patent_app_country] => US [patent_app_date] => 2024-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4825 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18403255 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19220000 [patent_doc_number] => 20240184704 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-06 [patent_title] => METHOD AND APPARATUS FOR READING CACHE DATA, AND STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 18/524706 [patent_app_country] => US [patent_app_date] => 2023-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9756 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18524706 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20331583 [patent_doc_number] => 12461860 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-04 [patent_title] => Physical address based set partitioning [patent_app_type] => utility [patent_app_number] => 18/522049 [patent_app_country] => US [patent_app_date] => 2023-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 16803 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18522049 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20027180 [patent_doc_number] => 20250165402 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-22 [patent_title] => Memory-Access Policies in Peripheral Device based on Memory Usage Characteristics [patent_app_type] => utility [patent_app_number] => 18/513563 [patent_app_country] => US [patent_app_date] => 2023-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1077 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18513563 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19174414 [patent_doc_number] => 20240160388 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-16 [patent_title] => MEMORY SYSTEM FOR SECURE READ AND WRITE OPERATIONS BASED ON PREDEFINED DATA PATTERNS [patent_app_type] => utility [patent_app_number] => 18/497860 [patent_app_country] => US [patent_app_date] => 2023-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3290 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18497860 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19878404 [patent_doc_number] => 20250110661 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-03 [patent_title] => SYSTEMS AND METHODS FOR ALLOCATING READ BUFFERS BASED ON READ DATA SIZES IN NON-VOLATILE STORAGE DEVICES [patent_app_type] => utility [patent_app_number] => 18/478293 [patent_app_country] => US [patent_app_date] => 2023-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10149 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18478293 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19878407 [patent_doc_number] => 20250110664 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-03 [patent_title] => EFFICIENT BUS TURNAROUND FOR MEMORY CONTROLLER [patent_app_type] => utility [patent_app_number] => 18/374153 [patent_app_country] => US [patent_app_date] => 2023-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7539 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18374153 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19159742 [patent_doc_number] => 20240152449 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-09 [patent_title] => READ AND WRITE ADDRESS TRANSLATION USING RESERVED MEMORY PAGES FOR MULTI-PAGE TRANSLATION UNITS [patent_app_type] => utility [patent_app_number] => 18/475966 [patent_app_country] => US [patent_app_date] => 2023-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25252 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18475966 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18819413 [patent_doc_number] => 20230393753 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => WEAR LEVELING IN SOLID STATE DRIVES [patent_app_type] => utility [patent_app_number] => 18/452020 [patent_app_country] => US [patent_app_date] => 2023-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5958 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18452020 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20689414 [patent_doc_number] => 12619563 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-05 [patent_title] => Dynamic random-access memory (DRAM) configured for block transfers and method thereof [patent_app_type] => utility [patent_app_number] => 18/365793 [patent_app_country] => US [patent_app_date] => 2023-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3681 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 346 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18365793 [rel_patent_id] =>[rel_patent_doc_number] =>)