Search

Sidney Li

Examiner (ID: 5954, Phone: (571)270-5967 , Office: P/2136 )

Most Active Art Unit
2136
Art Unit(s)
2186, 2136, 2137
Total Applications
464
Issued Applications
361
Pending Applications
37
Abandoned Applications
76

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20331583 [patent_doc_number] => 12461860 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-04 [patent_title] => Physical address based set partitioning [patent_app_type] => utility [patent_app_number] => 18/522049 [patent_app_country] => US [patent_app_date] => 2023-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 16803 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18522049 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/522049
Physical address based set partitioning Nov 27, 2023 Issued
Array ( [id] => 20027180 [patent_doc_number] => 20250165402 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-22 [patent_title] => Memory-Access Policies in Peripheral Device based on Memory Usage Characteristics [patent_app_type] => utility [patent_app_number] => 18/513563 [patent_app_country] => US [patent_app_date] => 2023-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1077 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18513563 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/513563
Memory-Access Policies in Peripheral Device based on Memory Usage Characteristics Nov 18, 2023 Pending
Array ( [id] => 19174414 [patent_doc_number] => 20240160388 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-16 [patent_title] => MEMORY SYSTEM FOR SECURE READ AND WRITE OPERATIONS BASED ON PREDEFINED DATA PATTERNS [patent_app_type] => utility [patent_app_number] => 18/497860 [patent_app_country] => US [patent_app_date] => 2023-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3290 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18497860 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/497860
MEMORY SYSTEM FOR SECURE READ AND WRITE OPERATIONS BASED ON PREDEFINED DATA PATTERNS Oct 29, 2023 Pending
Array ( [id] => 19878404 [patent_doc_number] => 20250110661 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-03 [patent_title] => SYSTEMS AND METHODS FOR ALLOCATING READ BUFFERS BASED ON READ DATA SIZES IN NON-VOLATILE STORAGE DEVICES [patent_app_type] => utility [patent_app_number] => 18/478293 [patent_app_country] => US [patent_app_date] => 2023-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10149 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18478293 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/478293
Systems and methods for allocating read buffers based on read data sizes in non-volatile storage devices Sep 28, 2023 Issued
Array ( [id] => 19878407 [patent_doc_number] => 20250110664 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-03 [patent_title] => EFFICIENT BUS TURNAROUND FOR MEMORY CONTROLLER [patent_app_type] => utility [patent_app_number] => 18/374153 [patent_app_country] => US [patent_app_date] => 2023-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7539 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18374153 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/374153
EFFICIENT BUS TURNAROUND FOR MEMORY CONTROLLER Sep 27, 2023 Pending
Array ( [id] => 19159742 [patent_doc_number] => 20240152449 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-09 [patent_title] => READ AND WRITE ADDRESS TRANSLATION USING RESERVED MEMORY PAGES FOR MULTI-PAGE TRANSLATION UNITS [patent_app_type] => utility [patent_app_number] => 18/475966 [patent_app_country] => US [patent_app_date] => 2023-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25252 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18475966 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/475966
Read and write address translation using reserved memory pages for multi-page translation units Sep 26, 2023 Issued
Array ( [id] => 18819413 [patent_doc_number] => 20230393753 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => WEAR LEVELING IN SOLID STATE DRIVES [patent_app_type] => utility [patent_app_number] => 18/452020 [patent_app_country] => US [patent_app_date] => 2023-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5958 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18452020 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/452020
WEAR LEVELING IN SOLID STATE DRIVES Aug 17, 2023 Pending
Array ( [id] => 19036531 [patent_doc_number] => 20240086346 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-14 [patent_title] => DYNAMIC RANDOM-ACCESS MEMORY (DRAM) CONFIGURED FOR BLOCK TRANSFERS AND METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/365793 [patent_app_country] => US [patent_app_date] => 2023-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8392 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18365793 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/365793
DYNAMIC RANDOM-ACCESS MEMORY (DRAM) CONFIGURED FOR BLOCK TRANSFERS AND METHOD THEREOF Aug 3, 2023 Pending
Array ( [id] => 18881424 [patent_doc_number] => 20240004793 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-04 [patent_title] => SHADOW CACHES FOR LEVEL 2 CACHE CONTROLLER [patent_app_type] => utility [patent_app_number] => 18/362005 [patent_app_country] => US [patent_app_date] => 2023-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16088 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18362005 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/362005
SHADOW CACHES FOR LEVEL 2 CACHE CONTROLLER Jul 30, 2023 Pending
Array ( [id] => 19725887 [patent_doc_number] => 20250028638 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-23 [patent_title] => SYSTEMS AND METHODS FOR CACHE FILTERING [patent_app_type] => utility [patent_app_number] => 18/355571 [patent_app_country] => US [patent_app_date] => 2023-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11292 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18355571 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/355571
Systems and methods for cache filtering Jul 19, 2023 Issued
Array ( [id] => 19686405 [patent_doc_number] => 20250004950 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => TRANSLATION LOOKASIDE BUFFER PROBING PREVENTION [patent_app_type] => utility [patent_app_number] => 18/344951 [patent_app_country] => US [patent_app_date] => 2023-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7678 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18344951 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/344951
Translation lookaside buffer probing prevention Jun 29, 2023 Issued
Array ( [id] => 18727780 [patent_doc_number] => 20230342073 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-26 [patent_title] => MEMORY EXPANDER, HETEROGENEOUS COMPUTING DEVICE USING MEMORY EXPANDER, AND OPERATION METHOD OF HETEROGENOUS COMPUTING [patent_app_type] => utility [patent_app_number] => 18/344837 [patent_app_country] => US [patent_app_date] => 2023-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15972 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18344837 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/344837
Memory expander, heterogeneous computing device using memory expander, and operation method of heterogenous computing Jun 28, 2023 Issued
Array ( [id] => 19267685 [patent_doc_number] => 20240211388 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => ELECTRONIC DEVICE FOR TIMEOUT PREVENTION AND OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/340413 [patent_app_country] => US [patent_app_date] => 2023-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10213 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18340413 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/340413
ELECTRONIC DEVICE FOR TIMEOUT PREVENTION AND OPERATION METHOD THEREOF Jun 22, 2023 Pending
Array ( [id] => 19313028 [patent_doc_number] => 12038840 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-16 [patent_title] => Multi-level cache security [patent_app_type] => utility [patent_app_number] => 18/334740 [patent_app_country] => US [patent_app_date] => 2023-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 18335 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 303 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18334740 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/334740
Multi-level cache security Jun 13, 2023 Issued
Array ( [id] => 19152570 [patent_doc_number] => 11977481 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-07 [patent_title] => Controller for controlling non-volatile semiconductor memory and method of controlling non-volatile semiconductor memory [patent_app_type] => utility [patent_app_number] => 18/310597 [patent_app_country] => US [patent_app_date] => 2023-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 48 [patent_no_of_words] => 37402 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18310597 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/310597
Controller for controlling non-volatile semiconductor memory and method of controlling non-volatile semiconductor memory May 1, 2023 Issued
Array ( [id] => 18695119 [patent_doc_number] => 20230325537 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-12 [patent_title] => MEMORY ACCESS GATE [patent_app_type] => utility [patent_app_number] => 18/136250 [patent_app_country] => US [patent_app_date] => 2023-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11957 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18136250 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/136250
MEMORY ACCESS GATE Apr 17, 2023 Pending
Array ( [id] => 19810992 [patent_doc_number] => 12242384 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-04 [patent_title] => Compression aware prefetch [patent_app_type] => utility [patent_app_number] => 18/102152 [patent_app_country] => US [patent_app_date] => 2023-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5527 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18102152 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/102152
Compression aware prefetch Jan 26, 2023 Issued
Array ( [id] => 18378166 [patent_doc_number] => 20230153253 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-18 [patent_title] => ACCESS TO DATA STORED IN QUARANTINED MEMORY MEDIA [patent_app_type] => utility [patent_app_number] => 18/098831 [patent_app_country] => US [patent_app_date] => 2023-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8332 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18098831 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/098831
Access to data stored in quarantined memory media Jan 18, 2023 Issued
Array ( [id] => 18377918 [patent_doc_number] => 20230153005 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-18 [patent_title] => Block Storage Device and Method for Data Compression [patent_app_type] => utility [patent_app_number] => 18/156824 [patent_app_country] => US [patent_app_date] => 2023-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5001 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18156824 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/156824
Block Storage Device and Method for Data Compression Jan 18, 2023 Pending
Array ( [id] => 19283941 [patent_doc_number] => 20240220417 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => SEGMENTED NON-CONTIGUOUS REVERSE MAP TABLE [patent_app_type] => utility [patent_app_number] => 18/090631 [patent_app_country] => US [patent_app_date] => 2022-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11817 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18090631 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/090631
Segmented non-contiguous reverse map table Dec 28, 2022 Issued
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