Sidney Li

Array ( [id] => 19152583 [patent_doc_number] => 11977494 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-07 [patent_title] => Providing a secure communication channel between kernel and user mode components [patent_app_type] => utility [patent_app_number] => 17/718449 [patent_app_country] => US [patent_app_date] => 2022-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6791 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17718449 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19506524 [patent_doc_number] => 12117944 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-15 [patent_title] => Systems, methods, and devices for queue management with a coherent interface [patent_app_type] => utility [patent_app_number] => 17/712066 [patent_app_country] => US [patent_app_date] => 2022-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 9442 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17712066 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17915757 [patent_doc_number] => 20220318153 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-06 [patent_title] => SYSTEMS AND METHODS FOR PROCESSING ASYNCHRONOUS RESET EVENTS WHILE MAINTAINING PERSISTENT MEMORY STATE [patent_app_type] => utility [patent_app_number] => 17/704903 [patent_app_country] => US [patent_app_date] => 2022-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11278 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17704903 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18720111 [patent_doc_number] => 11797456 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-24 [patent_title] => Systems and methods for coordinating persistent cache flushing [patent_app_type] => utility [patent_app_number] => 17/704909 [patent_app_country] => US [patent_app_date] => 2022-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11279 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17704909 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18889512 [patent_doc_number] => 11868282 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-01-09 [patent_title] => Network device using cache techniques to process control signals [patent_app_type] => utility [patent_app_number] => 17/698196 [patent_app_country] => US [patent_app_date] => 2022-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4746 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17698196 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19506071 [patent_doc_number] => 12117487 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-15 [patent_title] => Protection of the content of a fuse memory [patent_app_type] => utility [patent_app_number] => 17/654918 [patent_app_country] => US [patent_app_date] => 2022-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5013 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17654918 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18493451 [patent_doc_number] => 11698869 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-07-11 [patent_title] => Computing an authentication tag for partial transfers scheduled across multiple direct memory access (DMA) engines [patent_app_type] => utility [patent_app_number] => 17/654359 [patent_app_country] => US [patent_app_date] => 2022-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 12955 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17654359 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18414916 [patent_doc_number] => 11669458 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-06 [patent_title] => Computer-readable recording medium storing adjustment program and adjustment method [patent_app_type] => utility [patent_app_number] => 17/690041 [patent_app_country] => US [patent_app_date] => 2022-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 10587 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17690041 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17675073 [patent_doc_number] => 20220188240 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-16 [patent_title] => ELASTIC BUFFER IN A MEMORY SUB-SYSTEM FOR DEBUGGING INFORMATION [patent_app_type] => utility [patent_app_number] => 17/689857 [patent_app_country] => US [patent_app_date] => 2022-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8174 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17689857 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19212285 [patent_doc_number] => 12001347 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-04 [patent_title] => Memory storage device and method [patent_app_type] => utility [patent_app_number] => 17/653382 [patent_app_country] => US [patent_app_date] => 2022-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5056 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17653382 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18569128 [patent_doc_number] => 20230259464 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-17 [patent_title] => PREVENTING UNAUTHORIZED MEMORY ACCESS USING A PHYSICAL ADDRESS ACCESS PERMISSIONS TABLE [patent_app_type] => utility [patent_app_number] => 17/671144 [patent_app_country] => US [patent_app_date] => 2022-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11651 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17671144 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17629279 [patent_doc_number] => 20220164294 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-26 [patent_title] => CYBER SECURITY AND TAMPER DETECTION TECHNIQUES WITH A DISTRIBUTED PROCESSOR MEMORY CHIP [patent_app_type] => utility [patent_app_number] => 17/669642 [patent_app_country] => US [patent_app_date] => 2022-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 113363 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17669642 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17629270 [patent_doc_number] => 20220164285 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-26 [patent_title] => COMPENSATING FOR DRAM ACTIVATION PENALTIES [patent_app_type] => utility [patent_app_number] => 17/668240 [patent_app_country] => US [patent_app_date] => 2022-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 113371 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17668240 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17613902 [patent_doc_number] => 20220156182 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-19 [patent_title] => CONTROLLER FOR CONTROLLING NON-VOLATILE SEMICONDUCTOR MEMORY AND METHOD OF CONTROLLING NON-VOLATILE SEMICONDUCTOR MEMORY [patent_app_type] => utility [patent_app_number] => 17/590310 [patent_app_country] => US [patent_app_date] => 2022-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 37322 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17590310 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19475541 [patent_doc_number] => 12105630 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-01 [patent_title] => Compile time logic for inserting a buffer between a producer operation unit and a consumer operation unit in a dataflow graph [patent_app_type] => utility [patent_app_number] => 17/582421 [patent_app_country] => US [patent_app_date] => 2022-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 11489 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17582421 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18513115 [patent_doc_number] => 20230229340 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-20 [patent_title] => PERFORMING MEMORY ACCESS OPERATIONS BASED ON QUAD-LEVEL CELL TO SINGLE-LEVEL CELL MAPPING TABLE [patent_app_type] => utility [patent_app_number] => 17/578341 [patent_app_country] => US [patent_app_date] => 2022-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9821 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17578341 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18826520 [patent_doc_number] => 11841796 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-12 [patent_title] => Scratchpad memory in a cache [patent_app_type] => utility [patent_app_number] => 17/569336 [patent_app_country] => US [patent_app_date] => 2022-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 20638 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17569336 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18414908 [patent_doc_number] => 11669450 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-06 [patent_title] => Computer including cache used in plural different data sizes and control method of computer [patent_app_type] => utility [patent_app_number] => 17/645839 [patent_app_country] => US [patent_app_date] => 2021-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 9963 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17645839 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18471399 [patent_doc_number] => 20230205685 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => READ ALL ZEROS OR RANDOM DATA UPON A FIRST READ FROM VOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 17/560635 [patent_app_country] => US [patent_app_date] => 2021-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11377 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17560635 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17675299 [patent_doc_number] => 20220188466 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-16 [patent_title] => MEMORY ACCESS GATE [patent_app_type] => utility [patent_app_number] => 17/559484 [patent_app_country] => US [patent_app_date] => 2021-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11929 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17559484 [rel_patent_id] =>[rel_patent_doc_number] =>)