Search

Sidney Li

Examiner (ID: 5954, Phone: (571)270-5967 , Office: P/2136 )

Most Active Art Unit
2136
Art Unit(s)
2186, 2136, 2137
Total Applications
464
Issued Applications
361
Pending Applications
37
Abandoned Applications
76

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16577452 [patent_doc_number] => 20210011853 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-14 [patent_title] => GRAPHICS MEMORY EXTENDED WITH NONVOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 16/939158 [patent_app_country] => US [patent_app_date] => 2020-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 34208 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16939158 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/939158
Graphics memory extended with nonvolatile memory Jul 26, 2020 Issued
Array ( [id] => 17955222 [patent_doc_number] => 11481329 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-10-25 [patent_title] => Optimizing memory bandwidth in spatial architectures [patent_app_type] => utility [patent_app_number] => 16/929859 [patent_app_country] => US [patent_app_date] => 2020-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 11790 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16929859 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/929859
Optimizing memory bandwidth in spatial architectures Jul 14, 2020 Issued
Array ( [id] => 16393021 [patent_doc_number] => 20200333962 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-22 [patent_title] => Modularized Multi-Purpose Storage System [patent_app_type] => utility [patent_app_number] => 16/921033 [patent_app_country] => US [patent_app_date] => 2020-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11206 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16921033 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/921033
Modularized multi-purpose storage system Jul 5, 2020 Issued
Array ( [id] => 16393280 [patent_doc_number] => 20200334221 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-22 [patent_title] => CLASSIFICATION OF VIRTUALIZATION DATA [patent_app_type] => utility [patent_app_number] => 16/917591 [patent_app_country] => US [patent_app_date] => 2020-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26865 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16917591 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/917591
Classification of virtualization data Jun 29, 2020 Issued
Array ( [id] => 17294219 [patent_doc_number] => 20210390058 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-16 [patent_title] => DYNAMIC CACHE CONTROL MECHANISM [patent_app_type] => utility [patent_app_number] => 16/902909 [patent_app_country] => US [patent_app_date] => 2020-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23537 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16902909 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/902909
Dynamic cache control mechanism Jun 15, 2020 Issued
Array ( [id] => 17294095 [patent_doc_number] => 20210389934 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-16 [patent_title] => Memory Compiler Techniques [patent_app_type] => utility [patent_app_number] => 16/899502 [patent_app_country] => US [patent_app_date] => 2020-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7095 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16899502 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/899502
Memory compiler techniques Jun 10, 2020 Issued
Array ( [id] => 16371007 [patent_doc_number] => 10802762 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-10-13 [patent_title] => Systems and methods for asynchronous writing of synchronous write requests based on a dynamic write threshold [patent_app_type] => utility [patent_app_number] => 16/896062 [patent_app_country] => US [patent_app_date] => 2020-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9452 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16896062 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/896062
Systems and methods for asynchronous writing of synchronous write requests based on a dynamic write threshold Jun 7, 2020 Issued
Array ( [id] => 17261062 [patent_doc_number] => 20210374047 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-02 [patent_title] => METHODS, DEVICES, AND MEDIA FOR HARDWARE-SUPPORTED OBJECT METADATA RETRIEVAL [patent_app_type] => utility [patent_app_number] => 16/890772 [patent_app_country] => US [patent_app_date] => 2020-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12515 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16890772 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/890772
Methods, devices, and media for hardware-supported object metadata retrieval Jun 1, 2020 Issued
Array ( [id] => 17143864 [patent_doc_number] => 20210311877 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-07 [patent_title] => KEY-VALUE STORE ARCHITECTURE FOR KEY-VALUE DEVICES [patent_app_type] => utility [patent_app_number] => 16/886552 [patent_app_country] => US [patent_app_date] => 2020-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13466 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16886552 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/886552
Key-value store architecture for key-value devices May 27, 2020 Issued
Array ( [id] => 18547143 [patent_doc_number] => 11720495 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-08 [patent_title] => Multi-level cache security [patent_app_type] => utility [patent_app_number] => 16/882380 [patent_app_country] => US [patent_app_date] => 2020-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 18270 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16882380 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/882380
Multi-level cache security May 21, 2020 Issued
Array ( [id] => 16470383 [patent_doc_number] => 20200371920 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-26 [patent_title] => SHADOW CACHES FOR LEVEL 2 CACHE CONTROLLER [patent_app_type] => utility [patent_app_number] => 16/882202 [patent_app_country] => US [patent_app_date] => 2020-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16061 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16882202 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/882202
Shadow caches for level 2 cache controller May 21, 2020 Issued
Array ( [id] => 19971168 [patent_doc_number] => 12339779 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-24 [patent_title] => Method and apparatus for replacing data from near to far memory over a slow interconnect for oversubscribed irregular applications [patent_app_type] => utility [patent_app_number] => 17/594362 [patent_app_country] => US [patent_app_date] => 2020-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 2656 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 459 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17594362 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/594362
Method and apparatus for replacing data from near to far memory over a slow interconnect for oversubscribed irregular applications Apr 16, 2020 Issued
Array ( [id] => 17238282 [patent_doc_number] => 11182161 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-23 [patent_title] => Fractional or partial line usage prediction in a processor [patent_app_type] => utility [patent_app_number] => 16/849001 [patent_app_country] => US [patent_app_date] => 2020-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 10522 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16849001 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/849001
Fractional or partial line usage prediction in a processor Apr 14, 2020 Issued
Array ( [id] => 17325363 [patent_doc_number] => 11216375 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-04 [patent_title] => Data caching [patent_app_type] => utility [patent_app_number] => 16/849913 [patent_app_country] => US [patent_app_date] => 2020-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 22 [patent_no_of_words] => 10840 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16849913 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/849913
Data caching Apr 14, 2020 Issued
Array ( [id] => 16393043 [patent_doc_number] => 20200333984 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-22 [patent_title] => APPARATUS AND METHOD FOR CONTROLLING ACCESS TO MEMORY MODULE [patent_app_type] => utility [patent_app_number] => 16/847623 [patent_app_country] => US [patent_app_date] => 2020-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7822 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16847623 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/847623
Apparatus and method for controlling access to memory module Apr 12, 2020 Issued
Array ( [id] => 17499506 [patent_doc_number] => 11288212 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-29 [patent_title] => System, apparatus, and method for secure deduplication [patent_app_type] => utility [patent_app_number] => 16/846265 [patent_app_country] => US [patent_app_date] => 2020-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 27 [patent_no_of_words] => 29133 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16846265 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/846265
System, apparatus, and method for secure deduplication Apr 9, 2020 Issued
Array ( [id] => 17365049 [patent_doc_number] => 11232070 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-25 [patent_title] => Metadata compaction in a distributed storage system [patent_app_type] => utility [patent_app_number] => 16/828948 [patent_app_country] => US [patent_app_date] => 2020-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 11041 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16828948 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/828948
Metadata compaction in a distributed storage system Mar 23, 2020 Issued
Array ( [id] => 16833823 [patent_doc_number] => 11010074 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-18 [patent_title] => Adjustable performance parameters for SSDs [patent_app_type] => utility [patent_app_number] => 16/827585 [patent_app_country] => US [patent_app_date] => 2020-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7614 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16827585 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/827585
Adjustable performance parameters for SSDs Mar 22, 2020 Issued
Array ( [id] => 17879379 [patent_doc_number] => 11451415 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-20 [patent_title] => Circuitry for increasing bandwidth and reducing interference in memory signals [patent_app_type] => utility [patent_app_number] => 16/817764 [patent_app_country] => US [patent_app_date] => 2020-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6855 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16817764 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/817764
Circuitry for increasing bandwidth and reducing interference in memory signals Mar 12, 2020 Issued
Array ( [id] => 17099113 [patent_doc_number] => 20210286904 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-16 [patent_title] => MEMORY ACCESS GATE [patent_app_type] => utility [patent_app_number] => 16/814013 [patent_app_country] => US [patent_app_date] => 2020-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11887 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16814013 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/814013
Memory access gate Mar 9, 2020 Issued
Menu