Sidney Li

Array ( [id] => 17261062 [patent_doc_number] => 20210374047 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-02 [patent_title] => METHODS, DEVICES, AND MEDIA FOR HARDWARE-SUPPORTED OBJECT METADATA RETRIEVAL [patent_app_type] => utility [patent_app_number] => 16/890772 [patent_app_country] => US [patent_app_date] => 2020-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12515 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16890772 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17143864 [patent_doc_number] => 20210311877 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-07 [patent_title] => KEY-VALUE STORE ARCHITECTURE FOR KEY-VALUE DEVICES [patent_app_type] => utility [patent_app_number] => 16/886552 [patent_app_country] => US [patent_app_date] => 2020-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13466 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16886552 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16470383 [patent_doc_number] => 20200371920 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-26 [patent_title] => SHADOW CACHES FOR LEVEL 2 CACHE CONTROLLER [patent_app_type] => utility [patent_app_number] => 16/882202 [patent_app_country] => US [patent_app_date] => 2020-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16061 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16882202 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18547143 [patent_doc_number] => 11720495 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-08 [patent_title] => Multi-level cache security [patent_app_type] => utility [patent_app_number] => 16/882380 [patent_app_country] => US [patent_app_date] => 2020-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 18270 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16882380 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19971168 [patent_doc_number] => 12339779 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-24 [patent_title] => Method and apparatus for replacing data from near to far memory over a slow interconnect for oversubscribed irregular applications [patent_app_type] => utility [patent_app_number] => 17/594362 [patent_app_country] => US [patent_app_date] => 2020-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 2656 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 459 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17594362 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17325363 [patent_doc_number] => 11216375 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-04 [patent_title] => Data caching [patent_app_type] => utility [patent_app_number] => 16/849913 [patent_app_country] => US [patent_app_date] => 2020-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 22 [patent_no_of_words] => 10840 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16849913 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17238282 [patent_doc_number] => 11182161 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-23 [patent_title] => Fractional or partial line usage prediction in a processor [patent_app_type] => utility [patent_app_number] => 16/849001 [patent_app_country] => US [patent_app_date] => 2020-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 10522 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16849001 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16393043 [patent_doc_number] => 20200333984 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-22 [patent_title] => APPARATUS AND METHOD FOR CONTROLLING ACCESS TO MEMORY MODULE [patent_app_type] => utility [patent_app_number] => 16/847623 [patent_app_country] => US [patent_app_date] => 2020-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7822 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16847623 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17499506 [patent_doc_number] => 11288212 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-29 [patent_title] => System, apparatus, and method for secure deduplication [patent_app_type] => utility [patent_app_number] => 16/846265 [patent_app_country] => US [patent_app_date] => 2020-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 27 [patent_no_of_words] => 29133 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16846265 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17365049 [patent_doc_number] => 11232070 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-25 [patent_title] => Metadata compaction in a distributed storage system [patent_app_type] => utility [patent_app_number] => 16/828948 [patent_app_country] => US [patent_app_date] => 2020-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 11041 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16828948 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16833823 [patent_doc_number] => 11010074 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-18 [patent_title] => Adjustable performance parameters for SSDs [patent_app_type] => utility [patent_app_number] => 16/827585 [patent_app_country] => US [patent_app_date] => 2020-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7614 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16827585 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17879379 [patent_doc_number] => 11451415 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-20 [patent_title] => Circuitry for increasing bandwidth and reducing interference in memory signals [patent_app_type] => utility [patent_app_number] => 16/817764 [patent_app_country] => US [patent_app_date] => 2020-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6855 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16817764 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17099113 [patent_doc_number] => 20210286904 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-16 [patent_title] => MEMORY ACCESS GATE [patent_app_type] => utility [patent_app_number] => 16/814013 [patent_app_country] => US [patent_app_date] => 2020-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11887 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16814013 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17084178 [patent_doc_number] => 20210279184 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-09 [patent_title] => PROVIDING A SECURE COMMUNICATION CHANNEL BETWEEN KERNEL AND USER MODE COMPONENTS [patent_app_type] => utility [patent_app_number] => 16/809706 [patent_app_country] => US [patent_app_date] => 2020-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6735 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16809706 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17283150 [patent_doc_number] => 11200179 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-14 [patent_title] => Facilitating sequential reads in memory sub-systems [patent_app_type] => utility [patent_app_number] => 16/801949 [patent_app_country] => US [patent_app_date] => 2020-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6697 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16801949 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20273661 [patent_doc_number] => 12443443 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-14 [patent_title] => Workload scheduler for memory allocation [patent_app_type] => utility [patent_app_number] => 16/799745 [patent_app_country] => US [patent_app_date] => 2020-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 9542 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16799745 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17209560 [patent_doc_number] => 11169933 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-09 [patent_title] => Integration of application indicated maximum time to cache for a two-tiered cache management mechanism [patent_app_type] => utility [patent_app_number] => 16/790310 [patent_app_country] => US [patent_app_date] => 2020-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7873 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16790310 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17194940 [patent_doc_number] => 11163697 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-02 [patent_title] => Using a memory subsystem for storage of modified tracks from a cache [patent_app_type] => utility [patent_app_number] => 16/746473 [patent_app_country] => US [patent_app_date] => 2020-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7126 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16746473 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17325365 [patent_doc_number] => 11216377 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-04 [patent_title] => Hardware accelerator automatic detection of software process migration [patent_app_type] => utility [patent_app_number] => 16/719356 [patent_app_country] => US [patent_app_date] => 2019-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4451 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16719356 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17528702 [patent_doc_number] => 11301390 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-12 [patent_title] => Elastic buffer in a memory sub-system for debugging information [patent_app_type] => utility [patent_app_number] => 16/719765 [patent_app_country] => US [patent_app_date] => 2019-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8145 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16719765 [rel_patent_id] =>[rel_patent_doc_number] =>)