
Siegfried H Grimm
Examiner (ID: 11239)
| Most Active Art Unit | 2502 |
| Art Unit(s) | 2811, 2899, 2817, 2604, 2103, 2502, 2504, 2607 |
| Total Applications | 2132 |
| Issued Applications | 1976 |
| Pending Applications | 60 |
| Abandoned Applications | 96 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4379261
[patent_doc_number] => 06288614
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-09-11
[patent_title] => 'Phase-locked loop with improvements on phase jitter, MTIE tracking speed and locking speed'
[patent_app_type] => 1
[patent_app_number] => 9/564940
[patent_app_country] => US
[patent_app_date] => 2000-05-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 9221
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 364
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/288/06288614.pdf
[firstpage_image] =>[orig_patent_app_number] => 564940
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/564940 | Phase-locked loop with improvements on phase jitter, MTIE tracking speed and locking speed | May 3, 2000 | Issued |
Array
(
[id] => 4312839
[patent_doc_number] => 06326860
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-12-04
[patent_title] => 'Amplitude modulator capable of minimizing power leakage to adjacent channels'
[patent_app_type] => 1
[patent_app_number] => 9/563889
[patent_app_country] => US
[patent_app_date] => 2000-05-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 9
[patent_no_of_words] => 6395
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 194
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/326/06326860.pdf
[firstpage_image] =>[orig_patent_app_number] => 563889
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/563889 | Amplitude modulator capable of minimizing power leakage to adjacent channels | May 2, 2000 | Issued |
Array
(
[id] => 4303189
[patent_doc_number] => 06181211
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-01-30
[patent_title] => 'Automatic tuning of a VCO in a PLL'
[patent_app_type] => 1
[patent_app_number] => 9/525181
[patent_app_country] => US
[patent_app_date] => 2000-03-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 9
[patent_no_of_words] => 4016
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 186
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/181/06181211.pdf
[firstpage_image] =>[orig_patent_app_number] => 525181
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/525181 | Automatic tuning of a VCO in a PLL | Mar 13, 2000 | Issued |
Array
(
[id] => 4092163
[patent_doc_number] => 06163232
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-12-19
[patent_title] => 'Frequency/phase modulator using a digital synthesis circuit in a phase locked loop'
[patent_app_type] => 1
[patent_app_number] => 9/524234
[patent_app_country] => US
[patent_app_date] => 2000-03-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 3778
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 215
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/163/06163232.pdf
[firstpage_image] =>[orig_patent_app_number] => 524234
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/524234 | Frequency/phase modulator using a digital synthesis circuit in a phase locked loop | Mar 12, 2000 | Issued |
Array
(
[id] => 4303240
[patent_doc_number] => 06181215
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-01-30
[patent_title] => 'Quartz oscillator circuit having synchronously switched frequency adjusting capacitors'
[patent_app_type] => 1
[patent_app_number] => 9/519542
[patent_app_country] => US
[patent_app_date] => 2000-03-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 2809
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/181/06181215.pdf
[firstpage_image] =>[orig_patent_app_number] => 519542
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/519542 | Quartz oscillator circuit having synchronously switched frequency adjusting capacitors | Mar 5, 2000 | Issued |
| 09/516559 | Crystal oscillator circuit having low power consumption | Feb 28, 2000 | Abandoned |
Array
(
[id] => 4376288
[patent_doc_number] => 06275115
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-08-14
[patent_title] => 'PLL circuit having current control oscillator receiving the sum of two control currents'
[patent_app_type] => 1
[patent_app_number] => 9/515324
[patent_app_country] => US
[patent_app_date] => 2000-02-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 3228
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/275/06275115.pdf
[firstpage_image] =>[orig_patent_app_number] => 515324
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/515324 | PLL circuit having current control oscillator receiving the sum of two control currents | Feb 28, 2000 | Issued |
Array
(
[id] => 4140240
[patent_doc_number] => 06147563
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-11-14
[patent_title] => 'Coupled cavity oscillator producing output signals with a constant phase difference'
[patent_app_type] => 1
[patent_app_number] => 9/502529
[patent_app_country] => US
[patent_app_date] => 2000-02-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3409
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 177
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/147/06147563.pdf
[firstpage_image] =>[orig_patent_app_number] => 502529
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/502529 | Coupled cavity oscillator producing output signals with a constant phase difference | Feb 9, 2000 | Issued |
Array
(
[id] => 4414826
[patent_doc_number] => 06239660
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-05-29
[patent_title] => 'Step-controlled frequency synthesizer'
[patent_app_type] => 1
[patent_app_number] => 9/497991
[patent_app_country] => US
[patent_app_date] => 2000-02-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 2789
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/239/06239660.pdf
[firstpage_image] =>[orig_patent_app_number] => 497991
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/497991 | Step-controlled frequency synthesizer | Feb 3, 2000 | Issued |
Array
(
[id] => 1495761
[patent_doc_number] => 06342821
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-01-29
[patent_title] => 'Device capable of QPSK modulation and phase compensator for the same'
[patent_app_type] => B1
[patent_app_number] => 09/491431
[patent_app_country] => US
[patent_app_date] => 2000-01-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4084
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 67
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/342/06342821.pdf
[firstpage_image] =>[orig_patent_app_number] => 09491431
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/491431 | Device capable of QPSK modulation and phase compensator for the same | Jan 25, 2000 | Issued |
Array
(
[id] => 4337180
[patent_doc_number] => 06320474
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-11-20
[patent_title] => 'MOS-type capacitor and integrated circuit VCO using same'
[patent_app_type] => 1
[patent_app_number] => 9/473122
[patent_app_country] => US
[patent_app_date] => 1999-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 13
[patent_no_of_words] => 4937
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/320/06320474.pdf
[firstpage_image] =>[orig_patent_app_number] => 473122
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/473122 | MOS-type capacitor and integrated circuit VCO using same | Dec 27, 1999 | Issued |
Array
(
[id] => 4412675
[patent_doc_number] => 06271736
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-08-07
[patent_title] => 'Digital temperature-compensating crystal oscillator, and method for stabilizing frequency thereof'
[patent_app_type] => 1
[patent_app_number] => 9/472322
[patent_app_country] => US
[patent_app_date] => 1999-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 13
[patent_no_of_words] => 5699
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/271/06271736.pdf
[firstpage_image] =>[orig_patent_app_number] => 472322
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/472322 | Digital temperature-compensating crystal oscillator, and method for stabilizing frequency thereof | Dec 22, 1999 | Issued |
Array
(
[id] => 4403623
[patent_doc_number] => 06297704
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-10-02
[patent_title] => 'Oscillation circuits featuring coaxial resonators'
[patent_app_type] => 1
[patent_app_number] => 9/471140
[patent_app_country] => US
[patent_app_date] => 1999-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 29
[patent_no_of_words] => 11325
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/297/06297704.pdf
[firstpage_image] =>[orig_patent_app_number] => 471140
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/471140 | Oscillation circuits featuring coaxial resonators | Dec 22, 1999 | Issued |
Array
(
[id] => 4353845
[patent_doc_number] => 06285260
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-09-04
[patent_title] => 'Phase-locked loop having circuit for synchronizing starting points of two counters'
[patent_app_type] => 1
[patent_app_number] => 9/471711
[patent_app_country] => US
[patent_app_date] => 1999-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 2748
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 238
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/285/06285260.pdf
[firstpage_image] =>[orig_patent_app_number] => 471711
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/471711 | Phase-locked loop having circuit for synchronizing starting points of two counters | Dec 22, 1999 | Issued |
Array
(
[id] => 4416379
[patent_doc_number] => 06265949
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-07-24
[patent_title] => 'Phase compensation apparatus and method for a digital modulator'
[patent_app_type] => 1
[patent_app_number] => 9/469311
[patent_app_country] => US
[patent_app_date] => 1999-12-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 6172
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 56
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/265/06265949.pdf
[firstpage_image] =>[orig_patent_app_number] => 469311
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/469311 | Phase compensation apparatus and method for a digital modulator | Dec 21, 1999 | Issued |
Array
(
[id] => 4334434
[patent_doc_number] => 06329882
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-12-11
[patent_title] => 'Third-order self-biased phase-locked loop for low jitter applications'
[patent_app_type] => 1
[patent_app_number] => 9/468220
[patent_app_country] => US
[patent_app_date] => 1999-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 2024
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/329/06329882.pdf
[firstpage_image] =>[orig_patent_app_number] => 468220
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/468220 | Third-order self-biased phase-locked loop for low jitter applications | Dec 19, 1999 | Issued |
Array
(
[id] => 4416359
[patent_doc_number] => 06265948
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-07-24
[patent_title] => 'Image rejection in logic-based architecture for FSK modulation and demodulation'
[patent_app_type] => 1
[patent_app_number] => 9/467182
[patent_app_country] => US
[patent_app_date] => 1999-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 36
[patent_figures_cnt] => 36
[patent_no_of_words] => 11272
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/265/06265948.pdf
[firstpage_image] =>[orig_patent_app_number] => 467182
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/467182 | Image rejection in logic-based architecture for FSK modulation and demodulation | Dec 19, 1999 | Issued |
Array
(
[id] => 4379340
[patent_doc_number] => 06288618
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-09-11
[patent_title] => 'Logic-based architecture for FSK modulation and demodulation'
[patent_app_type] => 1
[patent_app_number] => 9/467183
[patent_app_country] => US
[patent_app_date] => 1999-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 36
[patent_figures_cnt] => 36
[patent_no_of_words] => 11400
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 49
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/288/06288618.pdf
[firstpage_image] =>[orig_patent_app_number] => 467183
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/467183 | Logic-based architecture for FSK modulation and demodulation | Dec 19, 1999 | Issued |
Array
(
[id] => 4268798
[patent_doc_number] => 06259330
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-07-10
[patent_title] => 'Ring oscillator having variable coarse and fine delays'
[patent_app_type] => 1
[patent_app_number] => 9/465709
[patent_app_country] => US
[patent_app_date] => 1999-12-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 3404
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/259/06259330.pdf
[firstpage_image] =>[orig_patent_app_number] => 465709
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/465709 | Ring oscillator having variable coarse and fine delays | Dec 16, 1999 | Issued |
Array
(
[id] => 4268770
[patent_doc_number] => 06259328
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-07-10
[patent_title] => 'Method and system for managing reference signals for network clock synchronization'
[patent_app_type] => 1
[patent_app_number] => 9/466352
[patent_app_country] => US
[patent_app_date] => 1999-12-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 11
[patent_no_of_words] => 9429
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 348
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/259/06259328.pdf
[firstpage_image] =>[orig_patent_app_number] => 466352
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/466352 | Method and system for managing reference signals for network clock synchronization | Dec 16, 1999 | Issued |