Sitaramarao S. Yechuri

Array ( [id] => 15352061 [patent_doc_number] => 20200013922 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-09 [patent_title] => SOLID STATE LIGHTING DEVICES WITH DIELECTRIC INSULATION AND METHODS OF MANUFACTURING [patent_app_type] => utility [patent_app_number] => 16/553720 [patent_app_country] => US [patent_app_date] => 2019-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3112 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16553720 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19138183 [patent_doc_number] => 11973159 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-30 [patent_title] => Photodetector [patent_app_type] => utility [patent_app_number] => 17/633717 [patent_app_country] => US [patent_app_date] => 2019-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3953 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17633717 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15442841 [patent_doc_number] => 20200035604 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-30 [patent_title] => MULTI-CHIP PACKAGE STRUCTURE HAVING CHIP INTERCONNECTION BRIDGE WHICH PROVIDES POWER CONNECTIONS BETWEEN CHIP AND PACKAGE SUBSTRATE [patent_app_type] => utility [patent_app_number] => 16/553453 [patent_app_country] => US [patent_app_date] => 2019-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8230 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16553453 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16464378 [patent_doc_number] => 10847743 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-24 [patent_title] => Electrode contacts [patent_app_type] => utility [patent_app_number] => 16/550896 [patent_app_country] => US [patent_app_date] => 2019-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 3200 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16550896 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16846159 [patent_doc_number] => 11018256 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-25 [patent_title] => Selective internal gate structure for ferroelectric semiconductor devices [patent_app_type] => utility [patent_app_number] => 16/549245 [patent_app_country] => US [patent_app_date] => 2019-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6397 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16549245 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16660639 [patent_doc_number] => 20210057276 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-25 [patent_title] => Melting Laser Anneal Of Epitaxy Regions [patent_app_type] => utility [patent_app_number] => 16/549213 [patent_app_country] => US [patent_app_date] => 2019-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8308 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16549213 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16928392 [patent_doc_number] => 11049884 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-29 [patent_title] => Display panel and method of manufacturing same, and display module [patent_app_type] => utility [patent_app_number] => 16/605213 [patent_app_country] => US [patent_app_date] => 2019-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 7250 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16605213 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16272319 [patent_doc_number] => 20200273807 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-27 [patent_title] => SEMICONDUCTOR PACKAGE WITH SILICON CRYSTAL STRUCTURE [patent_app_type] => utility [patent_app_number] => 16/513944 [patent_app_country] => US [patent_app_date] => 2019-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5413 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16513944 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16566902 [patent_doc_number] => 10892279 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-01-12 [patent_title] => NAND string containing separate hole and electron tunneling dielectric layers and methods for forming the same [patent_app_type] => utility [patent_app_number] => 16/514019 [patent_app_country] => US [patent_app_date] => 2019-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 45 [patent_no_of_words] => 16176 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16514019 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15154811 [patent_doc_number] => 20190355883 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-21 [patent_title] => LED LIGHT SOURCE, LED LIGHT SOURCE MANUFACTURING METHOD, AND DIRECT DISPLAY DEVICE THEREOF [patent_app_type] => utility [patent_app_number] => 16/510995 [patent_app_country] => US [patent_app_date] => 2019-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15934 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16510995 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17772463 [patent_doc_number] => 11404415 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-02 [patent_title] => Stacked-gate transistors [patent_app_type] => utility [patent_app_number] => 16/503982 [patent_app_country] => US [patent_app_date] => 2019-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2612 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16503982 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16001097 [patent_doc_number] => 20200176419 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-04 [patent_title] => WAFER RECONSTITUTION AND DIE-STITCHING [patent_app_type] => utility [patent_app_number] => 16/503806 [patent_app_country] => US [patent_app_date] => 2019-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8582 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 25 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16503806 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16835219 [patent_doc_number] => 11011479 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-18 [patent_title] => Protected electronic chip [patent_app_type] => utility [patent_app_number] => 16/503876 [patent_app_country] => US [patent_app_date] => 2019-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3977 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16503876 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16560478 [patent_doc_number] => 20210005627 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-07 [patent_title] => METHOD FOR ETCHING BOTTOM PUNCH-THROUGH OPENING IN A MEMORY FILM OF A MULTI-TIER THREE-DIMENSIONAL MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/503884 [patent_app_country] => US [patent_app_date] => 2019-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18832 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16503884 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17365969 [patent_doc_number] => 11233000 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-25 [patent_title] => Semiconductor package with inner lead pattern group and method for manufacturing the semiconductor package [patent_app_type] => utility [patent_app_number] => 16/503897 [patent_app_country] => US [patent_app_date] => 2019-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 9631 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16503897 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16746427 [patent_doc_number] => 10971428 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-06 [patent_title] => Semiconductor baseplates [patent_app_type] => utility [patent_app_number] => 16/447195 [patent_app_country] => US [patent_app_date] => 2019-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3526 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16447195 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16707688 [patent_doc_number] => 10957632 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-23 [patent_title] => Lead frame assembly for a semiconductor device [patent_app_type] => utility [patent_app_number] => 16/447123 [patent_app_country] => US [patent_app_date] => 2019-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 26 [patent_no_of_words] => 5857 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16447123 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17092896 [patent_doc_number] => 11121094 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-14 [patent_title] => Semiconductor devices with shield [patent_app_type] => utility [patent_app_number] => 16/447222 [patent_app_country] => US [patent_app_date] => 2019-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 29 [patent_no_of_words] => 6491 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16447222 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15300397 [patent_doc_number] => 20190393334 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-26 [patent_title] => Method for Producing a Semiconductor Arrangement [patent_app_type] => utility [patent_app_number] => 16/447207 [patent_app_country] => US [patent_app_date] => 2019-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12062 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -33 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16447207 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17040905 [patent_doc_number] => 20210257541 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-19 [patent_title] => MAGNETIC TUNNEL JUNCTION ELEMENT AND SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/252775 [patent_app_country] => US [patent_app_date] => 2019-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13561 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17252775 [rel_patent_id] =>[rel_patent_doc_number] =>)