Search

Sitaramarao S. Yechuri

Examiner (ID: 17123, Phone: (571)272-8764 , Office: P/2818 )

Most Active Art Unit
2818
Art Unit(s)
2821, 2818, 2893
Total Applications
939
Issued Applications
741
Pending Applications
92
Abandoned Applications
122

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15611611 [patent_doc_number] => 10586877 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-10 [patent_title] => Semiconductor device and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 16/165414 [patent_app_country] => US [patent_app_date] => 2018-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4386 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16165414 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/165414
Semiconductor device and method of manufacturing the same Oct 18, 2018 Issued
Array ( [id] => 16593909 [patent_doc_number] => 10903186 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-26 [patent_title] => Power electronic assemblies with solder layer and exterior coating, and methods of forming the same [patent_app_type] => utility [patent_app_number] => 16/165563 [patent_app_country] => US [patent_app_date] => 2018-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5263 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16165563 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/165563
Power electronic assemblies with solder layer and exterior coating, and methods of forming the same Oct 18, 2018 Issued
Array ( [id] => 16047973 [patent_doc_number] => 10685869 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-16 [patent_title] => Semiconductor device and method of forming the same [patent_app_type] => utility [patent_app_number] => 16/165525 [patent_app_country] => US [patent_app_date] => 2018-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4806 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16165525 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/165525
Semiconductor device and method of forming the same Oct 18, 2018 Issued
Array ( [id] => 15807297 [patent_doc_number] => 20200126791 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-23 [patent_title] => HARDMASK STRESS, GRAIN, AND STRUCTURE ENGINEERING FOR ADVANCED MEMORY APPLICATIONS [patent_app_type] => utility [patent_app_number] => 16/165311 [patent_app_country] => US [patent_app_date] => 2018-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7874 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16165311 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/165311
Hardmask stress, grain, and structure engineering for advanced memory applications Oct 18, 2018 Issued
Array ( [id] => 14221665 [patent_doc_number] => 20190123217 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-25 [patent_title] => Microlens Having a Carrier-Free Optical Interference Filter [patent_app_type] => utility [patent_app_number] => 16/165556 [patent_app_country] => US [patent_app_date] => 2018-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9437 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16165556 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/165556
Microlens having a carrier-free optical interference filter Oct 18, 2018 Issued
Array ( [id] => 15808103 [patent_doc_number] => 20200127194 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-23 [patent_title] => EMBEDDED MAGNETIC TUNNEL JUNCTION PILLAR HAVING REDUCED HEIGHT AND UNIFORM CONTACT AREA [patent_app_type] => utility [patent_app_number] => 16/165352 [patent_app_country] => US [patent_app_date] => 2018-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6507 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16165352 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/165352
Embedded magnetic tunnel junction pillar having reduced height and uniform contact area Oct 18, 2018 Issued
Array ( [id] => 15955563 [patent_doc_number] => 10665698 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-26 [patent_title] => Reducing gate-induced-drain-leakage current in a transistor by forming an enhanced band gap layer at the channel-to-drain interface [patent_app_type] => utility [patent_app_number] => 16/165440 [patent_app_country] => US [patent_app_date] => 2018-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 20 [patent_no_of_words] => 9643 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16165440 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/165440
Reducing gate-induced-drain-leakage current in a transistor by forming an enhanced band gap layer at the channel-to-drain interface Oct 18, 2018 Issued
Array ( [id] => 14164153 [patent_doc_number] => 20190109179 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-11 [patent_title] => Solid State Tissue Equivalent Detector With Gate Electrodes [patent_app_type] => utility [patent_app_number] => 16/156568 [patent_app_country] => US [patent_app_date] => 2018-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3457 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16156568 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/156568
Solid state tissue equivalent detector with gate electrodes Oct 9, 2018 Issued
Array ( [id] => 13909363 [patent_doc_number] => 20190043886 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-07 [patent_title] => MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/149249 [patent_app_country] => US [patent_app_date] => 2018-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10521 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16149249 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/149249
Memory device Oct 1, 2018 Issued
Array ( [id] => 16464282 [patent_doc_number] => 10847645 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-24 [patent_title] => Transistor structures having a deep recessed P+ junction and methods for making same [patent_app_type] => utility [patent_app_number] => 16/148214 [patent_app_country] => US [patent_app_date] => 2018-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7934 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16148214 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/148214
Transistor structures having a deep recessed P+ junction and methods for making same Sep 30, 2018 Issued
Array ( [id] => 16464282 [patent_doc_number] => 10847645 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-24 [patent_title] => Transistor structures having a deep recessed P+ junction and methods for making same [patent_app_type] => utility [patent_app_number] => 16/148214 [patent_app_country] => US [patent_app_date] => 2018-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7934 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16148214 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/148214
Transistor structures having a deep recessed P+ junction and methods for making same Sep 30, 2018 Issued
Array ( [id] => 16464282 [patent_doc_number] => 10847645 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-24 [patent_title] => Transistor structures having a deep recessed P+ junction and methods for making same [patent_app_type] => utility [patent_app_number] => 16/148214 [patent_app_country] => US [patent_app_date] => 2018-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7934 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16148214 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/148214
Transistor structures having a deep recessed P+ junction and methods for making same Sep 30, 2018 Issued
Array ( [id] => 16464282 [patent_doc_number] => 10847645 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-24 [patent_title] => Transistor structures having a deep recessed P+ junction and methods for making same [patent_app_type] => utility [patent_app_number] => 16/148214 [patent_app_country] => US [patent_app_date] => 2018-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7934 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16148214 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/148214
Transistor structures having a deep recessed P+ junction and methods for making same Sep 30, 2018 Issued
Array ( [id] => 16339263 [patent_doc_number] => 10790232 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-29 [patent_title] => Controlling warp in semiconductor laminated substrates with conductive material layout and orientation [patent_app_type] => utility [patent_app_number] => 16/132382 [patent_app_country] => US [patent_app_date] => 2018-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 9295 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 363 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16132382 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/132382
Controlling warp in semiconductor laminated substrates with conductive material layout and orientation Sep 14, 2018 Issued
Array ( [id] => 15415405 [patent_doc_number] => 20200028025 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-23 [patent_title] => OPTOELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 16/132244 [patent_app_country] => US [patent_app_date] => 2018-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13238 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16132244 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/132244
Optoelectronic device and method for fabricating the same Sep 13, 2018 Issued
Array ( [id] => 16454260 [patent_doc_number] => 20200363686 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-19 [patent_title] => LIQUID CRYSTAL PANEL [patent_app_type] => utility [patent_app_number] => 16/314481 [patent_app_country] => US [patent_app_date] => 2018-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5214 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16314481 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/314481
Liquid crystal panel Sep 13, 2018 Issued
Array ( [id] => 14079621 [patent_doc_number] => 20190088698 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-21 [patent_title] => CAMERA MODULE [patent_app_type] => utility [patent_app_number] => 16/132260 [patent_app_country] => US [patent_app_date] => 2018-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2955 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16132260 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/132260
Camera module Sep 13, 2018 Issued
Array ( [id] => 14510029 [patent_doc_number] => 20190198669 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-27 [patent_title] => VERTICAL FIELD EFFECT TRANSISTOR HAVING TWO-DIMENSIONAL CHANNEL STRUCTURE [patent_app_type] => utility [patent_app_number] => 16/128995 [patent_app_country] => US [patent_app_date] => 2018-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5158 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16128995 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/128995
Vertical field effect transistor having two-dimensional channel structure Sep 11, 2018 Issued
Array ( [id] => 15984861 [patent_doc_number] => 10672770 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-02 [patent_title] => Semiconductor structure [patent_app_type] => utility [patent_app_number] => 16/128783 [patent_app_country] => US [patent_app_date] => 2018-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 10155 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16128783 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/128783
Semiconductor structure Sep 11, 2018 Issued
Array ( [id] => 14446475 [patent_doc_number] => 20190181111 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-13 [patent_title] => DRIVING INTEGRATED CIRCUIT AND DISPLAY DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 16/128740 [patent_app_country] => US [patent_app_date] => 2018-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7454 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16128740 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/128740
Driving integrated circuit and display device including the same Sep 11, 2018 Issued
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