Search

Smita S. Patel

Examiner (ID: 17046, Phone: (571)270-5837 , Office: P/1732 )

Most Active Art Unit
1732
Art Unit(s)
1732, 4162, 1793
Total Applications
483
Issued Applications
328
Pending Applications
38
Abandoned Applications
126

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16911498 [patent_doc_number] => 11043548 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-22 [patent_title] => Light-emitting display apparatus [patent_app_type] => utility [patent_app_number] => 16/398631 [patent_app_country] => US [patent_app_date] => 2019-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10025 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16398631 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/398631
Light-emitting display apparatus Apr 29, 2019 Issued
16/398753 RESIST UNDERLAYER COMPOSITIONS AND METHODS OF FORMING PATTERNS WITH SUCH COMPOSITIONS Apr 29, 2019 Abandoned
Array ( [id] => 15687871 [patent_doc_number] => 20200098599 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-26 [patent_title] => SUBSTRATE BONDING APPARATUS AND BONDING METHOD USING THE SAME [patent_app_type] => utility [patent_app_number] => 16/397552 [patent_app_country] => US [patent_app_date] => 2019-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5859 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16397552 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/397552
Substrate bonding apparatus and bonding method using the same Apr 28, 2019 Issued
Array ( [id] => 15672867 [patent_doc_number] => 10600674 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-24 [patent_title] => Semiconductor devices with back surface isolation [patent_app_type] => utility [patent_app_number] => 16/388458 [patent_app_country] => US [patent_app_date] => 2019-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 43 [patent_no_of_words] => 11830 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16388458 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/388458
Semiconductor devices with back surface isolation Apr 17, 2019 Issued
Array ( [id] => 17559085 [patent_doc_number] => 11315807 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-26 [patent_title] => Substrate pressing module, substrate pressing method, substrate treating apparatus including the substrate treating module, and the substrate treating method [patent_app_type] => utility [patent_app_number] => 16/387501 [patent_app_country] => US [patent_app_date] => 2019-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 6437 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16387501 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/387501
Substrate pressing module, substrate pressing method, substrate treating apparatus including the substrate treating module, and the substrate treating method Apr 16, 2019 Issued
Array ( [id] => 14691505 [patent_doc_number] => 20190244868 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-08 [patent_title] => METHOD AND STRUCTURE FOR CMOS METAL GATE STACK [patent_app_type] => utility [patent_app_number] => 16/383531 [patent_app_country] => US [patent_app_date] => 2019-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4914 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16383531 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/383531
Method and structure for CMOS metal gate stack Apr 11, 2019 Issued
Array ( [id] => 16617164 [patent_doc_number] => 20210035817 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-04 [patent_title] => METHODS FOR MANUFACTURING SEMICONDUCTOR DEVICE AND WIRING STRUTURE [patent_app_type] => utility [patent_app_number] => 17/041637 [patent_app_country] => US [patent_app_date] => 2019-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12592 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17041637 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/041637
Methods for manufacturing semiconductor device and wiring structure Mar 25, 2019 Issued
Array ( [id] => 16348116 [patent_doc_number] => 20200312767 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-01 [patent_title] => INORGANIC-BASED EMBEDDED-DIE LAYERS FOR MODULAR SEMICONDUCTIVE DEVICES [patent_app_type] => utility [patent_app_number] => 16/363698 [patent_app_country] => US [patent_app_date] => 2019-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8658 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16363698 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/363698
Inorganic-based embedded-die layers for modular semiconductive devices Mar 24, 2019 Issued
Array ( [id] => 14580969 [patent_doc_number] => 20190218093 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-18 [patent_title] => MONOLITHICALLY INTEGRATED MULTI-SENSOR DEVICE ON A SEMICONDUCTOR SUBSTRATE AND METHOD THEREFOR [patent_app_type] => utility [patent_app_number] => 16/360274 [patent_app_country] => US [patent_app_date] => 2019-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 29748 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16360274 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/360274
MONOLITHICALLY INTEGRATED MULTI-SENSOR DEVICE ON A SEMICONDUCTOR SUBSTRATE AND METHOD THEREFOR Mar 20, 2019 Abandoned
Array ( [id] => 14631229 [patent_doc_number] => 20190228984 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-25 [patent_title] => SEMICONDUCTOR DEVICE HAVING BIASING STRUCTURE FOR SELF-ISOLATING BURIED LAYER AND METHOD THEREFOR [patent_app_type] => utility [patent_app_number] => 16/353551 [patent_app_country] => US [patent_app_date] => 2019-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11150 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16353551 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/353551
Semiconductor device having biasing structure for self-isolating buried layer and method therefor Mar 13, 2019 Issued
Array ( [id] => 16988169 [patent_doc_number] => 11075354 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-27 [patent_title] => Display panel and method for manufacturing thereof [patent_app_type] => utility [patent_app_number] => 16/339383 [patent_app_country] => US [patent_app_date] => 2019-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 2575 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16339383 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/339383
Display panel and method for manufacturing thereof Mar 12, 2019 Issued
Array ( [id] => 14542441 [patent_doc_number] => 20190206842 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-04 [patent_title] => Semiconductor Device Having Through Silicon Vias [patent_app_type] => utility [patent_app_number] => 16/295380 [patent_app_country] => US [patent_app_date] => 2019-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7296 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16295380 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/295380
Method of forming a semiconductor device having through silicon vias Mar 6, 2019 Issued
Array ( [id] => 17971382 [patent_doc_number] => 11488931 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-01 [patent_title] => Encapsulated fan-in semiconductor package with heat spreader and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 16/971412 [patent_app_country] => US [patent_app_date] => 2019-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 12 [patent_no_of_words] => 3976 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16971412 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/971412
Encapsulated fan-in semiconductor package with heat spreader and method of manufacturing the same Feb 24, 2019 Issued
Array ( [id] => 14413855 [patent_doc_number] => 20190172771 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-06 [patent_title] => LDMOS Transistor [patent_app_type] => utility [patent_app_number] => 16/272545 [patent_app_country] => US [patent_app_date] => 2019-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7373 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16272545 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/272545
LDMOS transistor Feb 10, 2019 Issued
Array ( [id] => 15442631 [patent_doc_number] => 20200035499 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-30 [patent_title] => METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/250180 [patent_app_country] => US [patent_app_date] => 2019-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7884 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16250180 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/250180
Method of manufacturing semiconductor device Jan 16, 2019 Issued
Array ( [id] => 16653337 [patent_doc_number] => 10930530 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-23 [patent_title] => Methods and apparatus for wafer temperature measurement [patent_app_type] => utility [patent_app_number] => 16/249588 [patent_app_country] => US [patent_app_date] => 2019-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9587 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16249588 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/249588
Methods and apparatus for wafer temperature measurement Jan 15, 2019 Issued
Array ( [id] => 17122078 [patent_doc_number] => 11133219 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-28 [patent_title] => Method of processing a wafer [patent_app_type] => utility [patent_app_number] => 16/247895 [patent_app_country] => US [patent_app_date] => 2019-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 28 [patent_no_of_words] => 21770 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16247895 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/247895
Method of processing a wafer Jan 14, 2019 Issued
Array ( [id] => 14587741 [patent_doc_number] => 20190221479 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-18 [patent_title] => MANUFACTURING PROCESS OF ELEMENT CHIP [patent_app_type] => utility [patent_app_number] => 16/246627 [patent_app_country] => US [patent_app_date] => 2019-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7921 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16246627 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/246627
Manufacturing process of element chip Jan 13, 2019 Issued
Array ( [id] => 14691681 [patent_doc_number] => 20190244956 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-08 [patent_title] => REFERENCE VOLTAGE GENERATION DEVICE [patent_app_type] => utility [patent_app_number] => 16/240428 [patent_app_country] => US [patent_app_date] => 2019-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4910 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16240428 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/240428
Reference voltage generation device Jan 3, 2019 Issued
Array ( [id] => 15260233 [patent_doc_number] => 20190378850 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-12 [patent_title] => VERTICAL MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 16/239809 [patent_app_country] => US [patent_app_date] => 2019-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8940 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16239809 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/239809
VERTICAL MEMORY DEVICES Jan 3, 2019 Abandoned
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