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Son Luu Mai

Examiner (ID: 6998, Phone: (571)272-1786 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2818, 2511, 2827
Total Applications
3061
Issued Applications
2917
Pending Applications
43
Abandoned Applications
107

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17699962 [patent_doc_number] => 11373694 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-06-28 [patent_title] => Generic physical layer providing a unified architecture for interfacing with an external memory device and methods of interfacing with an external memory device [patent_app_type] => utility [patent_app_number] => 17/169430 [patent_app_country] => US [patent_app_date] => 2021-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 39 [patent_no_of_words] => 8885 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17169430 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/169430
Generic physical layer providing a unified architecture for interfacing with an external memory device and methods of interfacing with an external memory device Feb 5, 2021 Issued
Array ( [id] => 16858134 [patent_doc_number] => 20210158879 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-27 [patent_title] => MEMORY DEVICE WHICH GENERATES OPERATION VOLTAGES IN PARALLEL WITH RECEPTION OF AN ADDRESS [patent_app_type] => utility [patent_app_number] => 17/168822 [patent_app_country] => US [patent_app_date] => 2021-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14285 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17168822 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/168822
Memory device which generates operation voltages in parallel with reception of an address Feb 4, 2021 Issued
Array ( [id] => 16981196 [patent_doc_number] => 20210225433 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-22 [patent_title] => REFRESH-RELATED ACTIVATION IMPROVEMENTS [patent_app_type] => utility [patent_app_number] => 17/159706 [patent_app_country] => US [patent_app_date] => 2021-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 24821 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17159706 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/159706
Refresh-related activation improvements Jan 26, 2021 Issued
Array ( [id] => 18998931 [patent_doc_number] => 11915785 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-27 [patent_title] => Memory sub-system management based on dynamic control of wordline start voltage [patent_app_type] => utility [patent_app_number] => 17/415657 [patent_app_country] => US [patent_app_date] => 2021-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6714 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17415657 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/415657
Memory sub-system management based on dynamic control of wordline start voltage Jan 25, 2021 Issued
Array ( [id] => 17041361 [patent_doc_number] => 20210257997 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-19 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/148587 [patent_app_country] => US [patent_app_date] => 2021-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5793 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17148587 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/148587
Semiconductor device Jan 13, 2021 Issued
Array ( [id] => 17373426 [patent_doc_number] => 20220028478 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-27 [patent_title] => NON-VOLATILE MEMORY DEVICE, OPERATING METHOD THEREOF, CONTROLLER FOR CONTROLLING THE SAME, AND STORAGE DEVICE HAVING THE SAME [patent_app_type] => utility [patent_app_number] => 17/147851 [patent_app_country] => US [patent_app_date] => 2021-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14127 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17147851 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/147851
Non-volatile memory device, operating method thereof, controller for controlling the same, and storage device having the same Jan 12, 2021 Issued
Array ( [id] => 17332221 [patent_doc_number] => 11222689 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-11 [patent_title] => Multi-phase clock division [patent_app_type] => utility [patent_app_number] => 17/136760 [patent_app_country] => US [patent_app_date] => 2020-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 7515 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17136760 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/136760
Multi-phase clock division Dec 28, 2020 Issued
Array ( [id] => 17716374 [patent_doc_number] => 11380372 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-07-05 [patent_title] => Transferring data between DRAM and SRAM [patent_app_type] => utility [patent_app_number] => 17/124697 [patent_app_country] => US [patent_app_date] => 2020-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4828 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17124697 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/124697
Transferring data between DRAM and SRAM Dec 16, 2020 Issued
Array ( [id] => 17424545 [patent_doc_number] => 11258009 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-22 [patent_title] => Switching atomic transistor and method for operating same [patent_app_type] => utility [patent_app_number] => 17/123824 [patent_app_country] => US [patent_app_date] => 2020-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 9044 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17123824 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/123824
Switching atomic transistor and method for operating same Dec 15, 2020 Issued
Array ( [id] => 17660444 [patent_doc_number] => 20220180909 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-09 [patent_title] => LIMITING REGULATOR OVERSHOOT DURING POWER UP [patent_app_type] => utility [patent_app_number] => 17/114321 [patent_app_country] => US [patent_app_date] => 2020-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11164 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17114321 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/114321
Limiting regulator overshoot during power up Dec 6, 2020 Issued
Array ( [id] => 17195866 [patent_doc_number] => 11164631 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-02 [patent_title] => Nonvolatile memory device and operating method of the same [patent_app_type] => utility [patent_app_number] => 17/113939 [patent_app_country] => US [patent_app_date] => 2020-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 11444 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17113939 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/113939
Nonvolatile memory device and operating method of the same Dec 6, 2020 Issued
Array ( [id] => 17188518 [patent_doc_number] => 20210335403 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-28 [patent_title] => DELAYED LOCKED LOOP CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME [patent_app_type] => utility [patent_app_number] => 17/109567 [patent_app_country] => US [patent_app_date] => 2020-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9271 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 317 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17109567 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/109567
Delay locked loop circuit and semiconductor memory device having the same Dec 1, 2020 Issued
Array ( [id] => 17010650 [patent_doc_number] => 20210241811 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-05 [patent_title] => POWER MODE WAKE-UP FOR MEMORY ON DIFFERENT POWER DOMAINS [patent_app_type] => utility [patent_app_number] => 17/103294 [patent_app_country] => US [patent_app_date] => 2020-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4433 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17103294 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/103294
Power mode wake-up for memory on different power domains Nov 23, 2020 Issued
Array ( [id] => 18105725 [patent_doc_number] => 11545625 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-03 [patent_title] => Tapered memory cell profiles [patent_app_type] => utility [patent_app_number] => 17/100185 [patent_app_country] => US [patent_app_date] => 2020-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 13524 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17100185 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/100185
Tapered memory cell profiles Nov 19, 2020 Issued
Array ( [id] => 17152256 [patent_doc_number] => 11145343 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-10-12 [patent_title] => Method for controlling multi-cycle write leveling process in memory system [patent_app_type] => utility [patent_app_number] => 16/953560 [patent_app_country] => US [patent_app_date] => 2020-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 5942 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 289 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16953560 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/953560
Method for controlling multi-cycle write leveling process in memory system Nov 19, 2020 Issued
Array ( [id] => 17615085 [patent_doc_number] => 20220157365 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-19 [patent_title] => TIMING SIGNAL DELAY FOR A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/952804 [patent_app_country] => US [patent_app_date] => 2020-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13600 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16952804 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/952804
Timing signal delay for a memory device Nov 18, 2020 Issued
Array ( [id] => 17825542 [patent_doc_number] => 11430494 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-30 [patent_title] => DQS position adjustment method, controller and network device [patent_app_type] => utility [patent_app_number] => 17/097680 [patent_app_country] => US [patent_app_date] => 2020-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 22 [patent_no_of_words] => 18738 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17097680 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/097680
DQS position adjustment method, controller and network device Nov 12, 2020 Issued
Array ( [id] => 17925679 [patent_doc_number] => 11468938 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-11 [patent_title] => Memory with programmable refresh order and stagger time [patent_app_type] => utility [patent_app_number] => 17/096469 [patent_app_country] => US [patent_app_date] => 2020-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 12281 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17096469 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/096469
Memory with programmable refresh order and stagger time Nov 11, 2020 Issued
Array ( [id] => 17332218 [patent_doc_number] => 11222686 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-01-11 [patent_title] => Apparatuses and methods for controlling refresh timing [patent_app_type] => utility [patent_app_number] => 17/095978 [patent_app_country] => US [patent_app_date] => 2020-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 8022 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17095978 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/095978
Apparatuses and methods for controlling refresh timing Nov 11, 2020 Issued
Array ( [id] => 17599064 [patent_doc_number] => 20220148638 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-12 [patent_title] => APPARATUS WITH DATA-RATE-BASED VOLTAGE CONTROL MECHANISM AND METHODS FOR OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/094731 [patent_app_country] => US [patent_app_date] => 2020-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6250 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17094731 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/094731
Apparatus with data-rate-based voltage control mechanism and methods for operating the same Nov 9, 2020 Issued
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