Search

Son Luu Mai

Examiner (ID: 6998, Phone: (571)272-1786 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2818, 2511, 2827
Total Applications
3061
Issued Applications
2917
Pending Applications
43
Abandoned Applications
107

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6754598 [patent_doc_number] => 20030002374 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-02 [patent_title] => 'Charging a capacitance of a memory cell and charger' [patent_app_type] => new [patent_app_number] => 10/154019 [patent_app_country] => US [patent_app_date] => 2002-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7249 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20030002374.pdf [firstpage_image] =>[orig_patent_app_number] => 10154019 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/154019
Charging a capacitance of a memory cell and charger May 22, 2002 Issued
Array ( [id] => 6644058 [patent_doc_number] => 20030007392 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-09 [patent_title] => 'Method for reading and storing binary memory cell signals and circuit arrangement' [patent_app_type] => new [patent_app_number] => 10/152950 [patent_app_country] => US [patent_app_date] => 2002-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2677 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0007/20030007392.pdf [firstpage_image] =>[orig_patent_app_number] => 10152950 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/152950
Method for reading and storing binary memory cells signals and circuit arrangement May 20, 2002 Issued
Array ( [id] => 1291963 [patent_doc_number] => 06639839 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-28 [patent_title] => 'Sensing method for EEPROM refresh scheme' [patent_app_type] => B1 [patent_app_number] => 10/151150 [patent_app_country] => US [patent_app_date] => 2002-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1773 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/639/06639839.pdf [firstpage_image] =>[orig_patent_app_number] => 10151150 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/151150
Sensing method for EEPROM refresh scheme May 20, 2002 Issued
Array ( [id] => 1314877 [patent_doc_number] => 06618281 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-09 [patent_title] => 'Content addressable memory (CAM) with error checking and correction (ECC) capability' [patent_app_type] => B1 [patent_app_number] => 10/146154 [patent_app_country] => US [patent_app_date] => 2002-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 5173 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/618/06618281.pdf [firstpage_image] =>[orig_patent_app_number] => 10146154 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/146154
Content addressable memory (CAM) with error checking and correction (ECC) capability May 14, 2002 Issued
Array ( [id] => 1346300 [patent_doc_number] => 06594181 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-15 [patent_title] => 'System for reading a double-bit memory cell' [patent_app_type] => B1 [patent_app_number] => 10/143449 [patent_app_country] => US [patent_app_date] => 2002-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 5417 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/594/06594181.pdf [firstpage_image] =>[orig_patent_app_number] => 10143449 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/143449
System for reading a double-bit memory cell May 9, 2002 Issued
Array ( [id] => 1384076 [patent_doc_number] => 06567304 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-20 [patent_title] => 'Memory device and method for reliably reading multi-bit data from a write-many memory cell' [patent_app_type] => B1 [patent_app_number] => 10/144451 [patent_app_country] => US [patent_app_date] => 2002-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 21 [patent_no_of_words] => 4725 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/567/06567304.pdf [firstpage_image] =>[orig_patent_app_number] => 10144451 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/144451
Memory device and method for reliably reading multi-bit data from a write-many memory cell May 8, 2002 Issued
Array ( [id] => 1038940 [patent_doc_number] => 06873540 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-29 [patent_title] => 'Molecular memory cell' [patent_app_type] => utility [patent_app_number] => 10/139748 [patent_app_country] => US [patent_app_date] => 2002-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 6526 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/873/06873540.pdf [firstpage_image] =>[orig_patent_app_number] => 10139748 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/139748
Molecular memory cell May 6, 2002 Issued
Array ( [id] => 6546685 [patent_doc_number] => 20020163829 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-07 [patent_title] => 'Memory switch' [patent_app_type] => new [patent_app_number] => 10/139746 [patent_app_country] => US [patent_app_date] => 2002-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3489 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0163/20020163829.pdf [firstpage_image] =>[orig_patent_app_number] => 10139746 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/139746
Addressable and electrically reversible memory switch May 6, 2002 Issued
Array ( [id] => 7633734 [patent_doc_number] => 06657886 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-02 [patent_title] => 'Split local and continuous bitline for fast domino read SRAM' [patent_app_type] => B1 [patent_app_number] => 10/140549 [patent_app_country] => US [patent_app_date] => 2002-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2424 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 9 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/657/06657886.pdf [firstpage_image] =>[orig_patent_app_number] => 10140549 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/140549
Split local and continuous bitline for fast domino read SRAM May 6, 2002 Issued
Array ( [id] => 1376890 [patent_doc_number] => 06570797 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-27 [patent_title] => 'Design for test to emulate a read with worse case test pattern' [patent_app_type] => B1 [patent_app_number] => 10/140646 [patent_app_country] => US [patent_app_date] => 2002-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2005 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/570/06570797.pdf [firstpage_image] =>[orig_patent_app_number] => 10140646 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/140646
Design for test to emulate a read with worse case test pattern May 6, 2002 Issued
Array ( [id] => 1194860 [patent_doc_number] => 06731528 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-05-04 [patent_title] => 'Dual write cycle programmable conductor memory system and method of operation' [patent_app_type] => B2 [patent_app_number] => 10/137554 [patent_app_country] => US [patent_app_date] => 2002-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 6210 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/731/06731528.pdf [firstpage_image] =>[orig_patent_app_number] => 10137554 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/137554
Dual write cycle programmable conductor memory system and method of operation May 2, 2002 Issued
Array ( [id] => 1372575 [patent_doc_number] => 06574159 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-06-03 [patent_title] => 'Semiconductor memory device and testing method therefor' [patent_app_type] => B2 [patent_app_number] => 10/137352 [patent_app_country] => US [patent_app_date] => 2002-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 53 [patent_no_of_words] => 37347 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/574/06574159.pdf [firstpage_image] =>[orig_patent_app_number] => 10137352 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/137352
Semiconductor memory device and testing method therefor May 2, 2002 Issued
Array ( [id] => 7624524 [patent_doc_number] => 06724652 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-04-20 [patent_title] => 'Low remanence flux concentrator for MRAM devices' [patent_app_type] => B2 [patent_app_number] => 10/137500 [patent_app_country] => US [patent_app_date] => 2002-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 36 [patent_no_of_words] => 8561 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/724/06724652.pdf [firstpage_image] =>[orig_patent_app_number] => 10137500 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/137500
Low remanence flux concentrator for MRAM devices May 1, 2002 Issued
Array ( [id] => 1428285 [patent_doc_number] => 06507521 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-01-14 [patent_title] => 'Semiconductor memory system' [patent_app_type] => B2 [patent_app_number] => 10/136281 [patent_app_country] => US [patent_app_date] => 2002-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 13071 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/507/06507521.pdf [firstpage_image] =>[orig_patent_app_number] => 10136281 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/136281
Semiconductor memory system May 1, 2002 Issued
Array ( [id] => 6749122 [patent_doc_number] => 20030043642 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-06 [patent_title] => 'LOW VOLTAGE CHARGE PUMP APPARATUS AND METHOD' [patent_app_type] => new [patent_app_number] => 10/136742 [patent_app_country] => US [patent_app_date] => 2002-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4637 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0043/20030043642.pdf [firstpage_image] =>[orig_patent_app_number] => 10136742 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/136742
Low voltage charge pump apparatus and method Apr 29, 2002 Issued
Array ( [id] => 7633732 [patent_doc_number] => 06657888 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-02 [patent_title] => 'Application of high spin polarization materials in two terminal non-volatile bistable memory devices' [patent_app_type] => B1 [patent_app_number] => 10/135348 [patent_app_country] => US [patent_app_date] => 2002-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 4888 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 12 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/657/06657888.pdf [firstpage_image] =>[orig_patent_app_number] => 10135348 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/135348
Application of high spin polarization materials in two terminal non-volatile bistable memory devices Apr 29, 2002 Issued
Array ( [id] => 6507485 [patent_doc_number] => 20020191469 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-19 [patent_title] => 'Semiconductor device and method of the semiconductor device' [patent_app_type] => new [patent_app_number] => 10/132248 [patent_app_country] => US [patent_app_date] => 2002-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 13792 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0191/20020191469.pdf [firstpage_image] =>[orig_patent_app_number] => 10132248 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/132248
Semiconductor device in which a chip is supplied either a first voltage or a second voltage Apr 25, 2002 Issued
Array ( [id] => 1358370 [patent_doc_number] => 06580635 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-17 [patent_title] => 'Bitline splitter' [patent_app_type] => B1 [patent_app_number] => 10/133946 [patent_app_country] => US [patent_app_date] => 2002-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1506 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/580/06580635.pdf [firstpage_image] =>[orig_patent_app_number] => 10133946 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/133946
Bitline splitter Apr 24, 2002 Issued
Array ( [id] => 1413375 [patent_doc_number] => 06542393 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-01 [patent_title] => 'Dual-bank memory module with stacked DRAM chips having a concave-shaped re-route PCB in-between' [patent_app_type] => B1 [patent_app_number] => 10/063452 [patent_app_country] => US [patent_app_date] => 2002-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 4603 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/542/06542393.pdf [firstpage_image] =>[orig_patent_app_number] => 10063452 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/063452
Dual-bank memory module with stacked DRAM chips having a concave-shaped re-route PCB in-between Apr 23, 2002 Issued
Array ( [id] => 7623003 [patent_doc_number] => 06687162 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-03 [patent_title] => 'Dual reference cell for split-gate nonvolatile semiconductor memory' [patent_app_type] => B1 [patent_app_number] => 10/126450 [patent_app_country] => US [patent_app_date] => 2002-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4611 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/687/06687162.pdf [firstpage_image] =>[orig_patent_app_number] => 10126450 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/126450
Dual reference cell for split-gate nonvolatile semiconductor memory Apr 18, 2002 Issued
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