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Son Luu Mai

Examiner (ID: 18155)

Most Active Art Unit
2827
Art Unit(s)
2511, 2827, 2818
Total Applications
3063
Issued Applications
2917
Pending Applications
45
Abandoned Applications
107

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1342050 [patent_doc_number] => 06597608 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-07-22 [patent_title] => 'CODING CELL OF NONVOLATILE FERROELECTRIC MEMORY DEVICE AND OPERATING METHOD THEREOF, AND COLUMN REPAIR CIRCUIT OF NONVOLATILE FERROELECTRIC MEMORY DEVICE HAVING THE CODING CELL AND METHOD FOR REPAIRING COLUMN' [patent_app_type] => B2 [patent_app_number] => 10/163351 [patent_app_country] => US [patent_app_date] => 2002-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 18 [patent_no_of_words] => 9667 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/597/06597608.pdf [firstpage_image] =>[orig_patent_app_number] => 10163351 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/163351
CODING CELL OF NONVOLATILE FERROELECTRIC MEMORY DEVICE AND OPERATING METHOD THEREOF, AND COLUMN REPAIR CIRCUIT OF NONVOLATILE FERROELECTRIC MEMORY DEVICE HAVING THE CODING CELL AND METHOD FOR REPAIRING COLUMN Jun 6, 2002 Issued
Array ( [id] => 1247691 [patent_doc_number] => 06678184 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-01-13 [patent_title] => 'CAM cell having compare circuit formed over two active regions' [patent_app_type] => B2 [patent_app_number] => 10/163848 [patent_app_country] => US [patent_app_date] => 2002-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5520 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/678/06678184.pdf [firstpage_image] =>[orig_patent_app_number] => 10163848 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/163848
CAM cell having compare circuit formed over two active regions Jun 4, 2002 Issued
Array ( [id] => 1538560 [patent_doc_number] => 06490196 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-03 [patent_title] => 'Method for operating a nonvolatile memory having embedded word lines' [patent_app_type] => B1 [patent_app_number] => 10/064047 [patent_app_country] => US [patent_app_date] => 2002-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3083 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 288 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/490/06490196.pdf [firstpage_image] =>[orig_patent_app_number] => 10064047 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/064047
Method for operating a nonvolatile memory having embedded word lines Jun 3, 2002 Issued
Array ( [id] => 6754599 [patent_doc_number] => 20030002375 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-02 [patent_title] => 'Memory arrangement' [patent_app_type] => new [patent_app_number] => 10/161146 [patent_app_country] => US [patent_app_date] => 2002-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2382 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 10 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20030002375.pdf [firstpage_image] =>[orig_patent_app_number] => 10161146 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/161146
Memory arrangement with selectable memory sectors May 30, 2002 Issued
Array ( [id] => 1135683 [patent_doc_number] => 06788586 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-07 [patent_title] => 'Output buffer for a nonvolatile memory with output signal switching noise reduction, and nonvolatile memory comprising the same' [patent_app_type] => B2 [patent_app_number] => 10/161053 [patent_app_country] => US [patent_app_date] => 2002-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 4171 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/788/06788586.pdf [firstpage_image] =>[orig_patent_app_number] => 10161053 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/161053
Output buffer for a nonvolatile memory with output signal switching noise reduction, and nonvolatile memory comprising the same May 29, 2002 Issued
Array ( [id] => 1310753 [patent_doc_number] => 06621762 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-16 [patent_title] => 'Non-volatile delay register' [patent_app_type] => B1 [patent_app_number] => 10/159152 [patent_app_country] => US [patent_app_date] => 2002-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2723 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/621/06621762.pdf [firstpage_image] =>[orig_patent_app_number] => 10159152 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/159152
Non-volatile delay register May 28, 2002 Issued
Array ( [id] => 1275827 [patent_doc_number] => 06654291 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-11-25 [patent_title] => 'Electrically erasable programmable read-only memory and method of erasing select memory cells' [patent_app_type] => B2 [patent_app_number] => 10/155953 [patent_app_country] => US [patent_app_date] => 2002-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2931 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/654/06654291.pdf [firstpage_image] =>[orig_patent_app_number] => 10155953 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/155953
Electrically erasable programmable read-only memory and method of erasing select memory cells May 23, 2002 Issued
Array ( [id] => 6820737 [patent_doc_number] => 20030218898 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-27 [patent_title] => 'GROUPED PLATE LINE DRIVE ARCHITECTURE AND METHOD' [patent_app_type] => new [patent_app_number] => 10/154647 [patent_app_country] => US [patent_app_date] => 2002-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3119 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0218/20030218898.pdf [firstpage_image] =>[orig_patent_app_number] => 10154647 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/154647
Grouped plate line drive architecture and method May 23, 2002 Issued
Array ( [id] => 6754598 [patent_doc_number] => 20030002374 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-02 [patent_title] => 'Charging a capacitance of a memory cell and charger' [patent_app_type] => new [patent_app_number] => 10/154019 [patent_app_country] => US [patent_app_date] => 2002-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7249 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20030002374.pdf [firstpage_image] =>[orig_patent_app_number] => 10154019 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/154019
Charging a capacitance of a memory cell and charger May 22, 2002 Issued
Array ( [id] => 1291963 [patent_doc_number] => 06639839 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-28 [patent_title] => 'Sensing method for EEPROM refresh scheme' [patent_app_type] => B1 [patent_app_number] => 10/151150 [patent_app_country] => US [patent_app_date] => 2002-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1773 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/639/06639839.pdf [firstpage_image] =>[orig_patent_app_number] => 10151150 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/151150
Sensing method for EEPROM refresh scheme May 20, 2002 Issued
Array ( [id] => 6644058 [patent_doc_number] => 20030007392 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-09 [patent_title] => 'Method for reading and storing binary memory cell signals and circuit arrangement' [patent_app_type] => new [patent_app_number] => 10/152950 [patent_app_country] => US [patent_app_date] => 2002-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2677 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0007/20030007392.pdf [firstpage_image] =>[orig_patent_app_number] => 10152950 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/152950
Method for reading and storing binary memory cells signals and circuit arrangement May 20, 2002 Issued
Array ( [id] => 1314877 [patent_doc_number] => 06618281 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-09 [patent_title] => 'Content addressable memory (CAM) with error checking and correction (ECC) capability' [patent_app_type] => B1 [patent_app_number] => 10/146154 [patent_app_country] => US [patent_app_date] => 2002-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 5173 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/618/06618281.pdf [firstpage_image] =>[orig_patent_app_number] => 10146154 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/146154
Content addressable memory (CAM) with error checking and correction (ECC) capability May 14, 2002 Issued
Array ( [id] => 1346300 [patent_doc_number] => 06594181 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-15 [patent_title] => 'System for reading a double-bit memory cell' [patent_app_type] => B1 [patent_app_number] => 10/143449 [patent_app_country] => US [patent_app_date] => 2002-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 5417 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/594/06594181.pdf [firstpage_image] =>[orig_patent_app_number] => 10143449 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/143449
System for reading a double-bit memory cell May 9, 2002 Issued
Array ( [id] => 1384076 [patent_doc_number] => 06567304 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-20 [patent_title] => 'Memory device and method for reliably reading multi-bit data from a write-many memory cell' [patent_app_type] => B1 [patent_app_number] => 10/144451 [patent_app_country] => US [patent_app_date] => 2002-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 21 [patent_no_of_words] => 4725 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/567/06567304.pdf [firstpage_image] =>[orig_patent_app_number] => 10144451 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/144451
Memory device and method for reliably reading multi-bit data from a write-many memory cell May 8, 2002 Issued
Array ( [id] => 7633734 [patent_doc_number] => 06657886 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-02 [patent_title] => 'Split local and continuous bitline for fast domino read SRAM' [patent_app_type] => B1 [patent_app_number] => 10/140549 [patent_app_country] => US [patent_app_date] => 2002-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2424 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 9 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/657/06657886.pdf [firstpage_image] =>[orig_patent_app_number] => 10140549 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/140549
Split local and continuous bitline for fast domino read SRAM May 6, 2002 Issued
Array ( [id] => 1038940 [patent_doc_number] => 06873540 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-29 [patent_title] => 'Molecular memory cell' [patent_app_type] => utility [patent_app_number] => 10/139748 [patent_app_country] => US [patent_app_date] => 2002-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 6526 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/873/06873540.pdf [firstpage_image] =>[orig_patent_app_number] => 10139748 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/139748
Molecular memory cell May 6, 2002 Issued
Array ( [id] => 1376890 [patent_doc_number] => 06570797 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-27 [patent_title] => 'Design for test to emulate a read with worse case test pattern' [patent_app_type] => B1 [patent_app_number] => 10/140646 [patent_app_country] => US [patent_app_date] => 2002-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2005 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/570/06570797.pdf [firstpage_image] =>[orig_patent_app_number] => 10140646 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/140646
Design for test to emulate a read with worse case test pattern May 6, 2002 Issued
Array ( [id] => 6546685 [patent_doc_number] => 20020163829 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-07 [patent_title] => 'Memory switch' [patent_app_type] => new [patent_app_number] => 10/139746 [patent_app_country] => US [patent_app_date] => 2002-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3489 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0163/20020163829.pdf [firstpage_image] =>[orig_patent_app_number] => 10139746 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/139746
Addressable and electrically reversible memory switch May 6, 2002 Issued
Array ( [id] => 1372575 [patent_doc_number] => 06574159 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-06-03 [patent_title] => 'Semiconductor memory device and testing method therefor' [patent_app_type] => B2 [patent_app_number] => 10/137352 [patent_app_country] => US [patent_app_date] => 2002-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 53 [patent_no_of_words] => 37347 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/574/06574159.pdf [firstpage_image] =>[orig_patent_app_number] => 10137352 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/137352
Semiconductor memory device and testing method therefor May 2, 2002 Issued
Array ( [id] => 1194860 [patent_doc_number] => 06731528 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-05-04 [patent_title] => 'Dual write cycle programmable conductor memory system and method of operation' [patent_app_type] => B2 [patent_app_number] => 10/137554 [patent_app_country] => US [patent_app_date] => 2002-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 6210 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/731/06731528.pdf [firstpage_image] =>[orig_patent_app_number] => 10137554 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/137554
Dual write cycle programmable conductor memory system and method of operation May 2, 2002 Issued
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