Son Luu Mai

Array ( [id] => 6062002 [patent_doc_number] => 20020031038 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-14 [patent_title] => 'Semiconductor device that enables simultaneous read and write/read operation' [patent_app_type] => new [patent_app_number] => 09/987981 [patent_app_country] => US [patent_app_date] => 2001-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 48 [patent_figures_cnt] => 48 [patent_no_of_words] => 20839 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0031/20020031038.pdf [firstpage_image] =>[orig_patent_app_number] => 09987981 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1410105 [patent_doc_number] => 06545902 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-08 [patent_title] => 'Ferroelectric memory device' [patent_app_type] => B2 [patent_app_number] => 09/987590 [patent_app_country] => US [patent_app_date] => 2001-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 38 [patent_no_of_words] => 14812 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/545/06545902.pdf [firstpage_image] =>[orig_patent_app_number] => 09987590 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7644640 [patent_doc_number] => 06473333 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-29 [patent_title] => 'Storage circuit with layered structure element' [patent_app_type] => B1 [patent_app_number] => 09/986946 [patent_app_country] => US [patent_app_date] => 2001-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9050 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 9 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/473/06473333.pdf [firstpage_image] =>[orig_patent_app_number] => 09986946 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1511413 [patent_doc_number] => 06442088 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-27 [patent_title] => 'Semiconductor memory system, and access control method for semiconductor memory and semiconductor memory' [patent_app_type] => B1 [patent_app_number] => 09/986658 [patent_app_country] => US [patent_app_date] => 2001-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 8639 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/442/06442088.pdf [firstpage_image] =>[orig_patent_app_number] => 09986658 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1431645 [patent_doc_number] => 06504743 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-01-07 [patent_title] => 'Die architecture accommodating high-speed semiconductor devices' [patent_app_type] => B2 [patent_app_number] => 10/007571 [patent_app_country] => US [patent_app_date] => 2001-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3403 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/504/06504743.pdf [firstpage_image] =>[orig_patent_app_number] => 10007571 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5784780 [patent_doc_number] => 20020159299 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-31 [patent_title] => 'DATA TRANSFER CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT HAVING THE SAME' [patent_app_type] => new [patent_app_number] => 09/985350 [patent_app_country] => US [patent_app_date] => 2001-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8046 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0159/20020159299.pdf [firstpage_image] =>[orig_patent_app_number] => 09985350 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1507336 [patent_doc_number] => 06466475 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-15 [patent_title] => 'Uniform magnetic environment for cells in an MRAM array' [patent_app_type] => B1 [patent_app_number] => 10/000652 [patent_app_country] => US [patent_app_date] => 2001-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 6575 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/466/06466475.pdf [firstpage_image] =>[orig_patent_app_number] => 10000652 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6245354 [patent_doc_number] => 20020046318 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-18 [patent_title] => 'Flash eeprom system' [patent_app_type] => new [patent_app_number] => 10/000155 [patent_app_country] => US [patent_app_date] => 2001-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9595 [patent_no_of_claims] => 62 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20020046318.pdf [firstpage_image] =>[orig_patent_app_number] => 10000155 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5934633 [patent_doc_number] => 20020060921 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-23 [patent_title] => 'Die architecture accommodating high-speed semiconductor devices' [patent_app_type] => new [patent_app_number] => 09/999094 [patent_app_country] => US [patent_app_date] => 2001-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 3583 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0060/20020060921.pdf [firstpage_image] =>[orig_patent_app_number] => 09999094 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1482939 [patent_doc_number] => 06452849 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-17 [patent_title] => 'Semiconductor device with test mode for performing efficient calibration of measuring apparatus' [patent_app_type] => B1 [patent_app_number] => 09/983650 [patent_app_country] => US [patent_app_date] => 2001-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 23 [patent_no_of_words] => 8027 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/452/06452849.pdf [firstpage_image] =>[orig_patent_app_number] => 09983650 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1383973 [patent_doc_number] => 06567298 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-05-20 [patent_title] => 'Semiconductor memory device and control method thereof' [patent_app_type] => B2 [patent_app_number] => 09/983148 [patent_app_country] => US [patent_app_date] => 2001-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 16385 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/567/06567298.pdf [firstpage_image] =>[orig_patent_app_number] => 09983148 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1564176 [patent_doc_number] => 06438016 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-20 [patent_title] => 'Semiconductor memory having dual port cell supporting hidden refresh' [patent_app_type] => B1 [patent_app_number] => 10/027569 [patent_app_country] => US [patent_app_date] => 2001-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4866 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/438/06438016.pdf [firstpage_image] =>[orig_patent_app_number] => 10027569 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1425291 [patent_doc_number] => 06512708 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-28 [patent_title] => 'Placement and routing for wafer scale memory' [patent_app_type] => B1 [patent_app_number] => 09/981650 [patent_app_country] => US [patent_app_date] => 2001-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 40 [patent_no_of_words] => 9612 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/512/06512708.pdf [firstpage_image] =>[orig_patent_app_number] => 09981650 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6466759 [patent_doc_number] => 20020021607 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-21 [patent_title] => 'Device and method for margin testing a semiconductor memory by applying a stressing voltage simultaneously to complementary and true digit lines' [patent_app_type] => new [patent_app_number] => 09/977755 [patent_app_country] => US [patent_app_date] => 2001-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3167 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0021/20020021607.pdf [firstpage_image] =>[orig_patent_app_number] => 09977755 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6303921 [patent_doc_number] => 20020093864 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-18 [patent_title] => 'LOW-POWER SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => new [patent_app_number] => 09/976049 [patent_app_country] => US [patent_app_date] => 2001-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 28353 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0093/20020093864.pdf [firstpage_image] =>[orig_patent_app_number] => 09976049 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1470081 [patent_doc_number] => 06459648 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-01 [patent_title] => 'Fault-tolerant address logic for solid state memory' [patent_app_type] => B1 [patent_app_number] => 09/976748 [patent_app_country] => US [patent_app_date] => 2001-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 3992 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/459/06459648.pdf [firstpage_image] =>[orig_patent_app_number] => 09976748 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1582501 [patent_doc_number] => 06449194 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-10 [patent_title] => 'Multiplexer with dummy switches in normally off state to increase operating speed' [patent_app_type] => B1 [patent_app_number] => 09/972151 [patent_app_country] => US [patent_app_date] => 2001-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4337 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/449/06449194.pdf [firstpage_image] =>[orig_patent_app_number] => 09972151 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5827235 [patent_doc_number] => 20020067655 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-06 [patent_title] => 'Control and timing structure for a memory' [patent_app_type] => new [patent_app_number] => 09/972753 [patent_app_country] => US [patent_app_date] => 2001-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5362 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 282 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0067/20020067655.pdf [firstpage_image] =>[orig_patent_app_number] => 09972753 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1538622 [patent_doc_number] => 06490209 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-03 [patent_title] => 'Memory employing multiple enable/disable modes for redundant elements and testing method using same' [patent_app_type] => B1 [patent_app_number] => 09/968749 [patent_app_country] => US [patent_app_date] => 2001-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4650 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/490/06490209.pdf [firstpage_image] =>[orig_patent_app_number] => 09968749 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6673085 [patent_doc_number] => 20030058688 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-27 [patent_title] => 'Integrated circuit for concurent flash memory' [patent_app_type] => new [patent_app_number] => 09/966554 [patent_app_country] => US [patent_app_date] => 2001-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2966 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0058/20030058688.pdf [firstpage_image] =>[orig_patent_app_number] => 09966554 [rel_patent_id] =>[rel_patent_doc_number] =>)