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Son Luu Mai

Examiner (ID: 18155)

Most Active Art Unit
2827
Art Unit(s)
2511, 2827, 2818
Total Applications
3063
Issued Applications
2917
Pending Applications
45
Abandoned Applications
107

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1463777 [patent_doc_number] => 06392946 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'SDR and QDR converter and interface card, motherboard and memory module interface using the same' [patent_app_type] => B1 [patent_app_number] => 09/930746 [patent_app_country] => US [patent_app_date] => 2001-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 3400 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/392/06392946.pdf [firstpage_image] =>[orig_patent_app_number] => 09930746 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/930746
SDR and QDR converter and interface card, motherboard and memory module interface using the same Aug 13, 2001 Issued
Array ( [id] => 7639177 [patent_doc_number] => 06396740 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-28 [patent_title] => 'Reference cell circuit for split gate flash memory' [patent_app_type] => B1 [patent_app_number] => 09/928051 [patent_app_country] => US [patent_app_date] => 2001-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 2326 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 11 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/396/06396740.pdf [firstpage_image] =>[orig_patent_app_number] => 09928051 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/928051
Reference cell circuit for split gate flash memory Aug 9, 2001 Issued
Array ( [id] => 6466765 [patent_doc_number] => 20020021608 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-21 [patent_title] => 'Semiconductor memory device' [patent_app_type] => new [patent_app_number] => 09/923948 [patent_app_country] => US [patent_app_date] => 2001-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6181 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0021/20020021608.pdf [firstpage_image] =>[orig_patent_app_number] => 09923948 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/923948
Semiconductor memory device Aug 7, 2001 Issued
Array ( [id] => 1578391 [patent_doc_number] => 06469953 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-22 [patent_title] => 'Latch circuit' [patent_app_type] => B1 [patent_app_number] => 09/925148 [patent_app_country] => US [patent_app_date] => 2001-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2337 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/469/06469953.pdf [firstpage_image] =>[orig_patent_app_number] => 09925148 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/925148
Latch circuit Aug 7, 2001 Issued
Array ( [id] => 6272734 [patent_doc_number] => 20020105847 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-08 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE CAPABLE OF SWITCHING REFERENCE VOLTAGE FOR GENERATING INTERMEDIATE VOLTAGE' [patent_app_type] => new [patent_app_number] => 09/923454 [patent_app_country] => US [patent_app_date] => 2001-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 11565 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0105/20020105847.pdf [firstpage_image] =>[orig_patent_app_number] => 09923454 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/923454
Semiconductor memory device capable of switching reference voltage for generating intermediate voltage Aug 7, 2001 Issued
Array ( [id] => 1504350 [patent_doc_number] => 06487123 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-26 [patent_title] => 'Semiconductor integrated circuit, ink cartridge having the semiconductor integrated circuit, and inkjet recording device having the ink cartridge attached' [patent_app_type] => B1 [patent_app_number] => 09/857451 [patent_app_country] => US [patent_app_date] => 2001-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 6859 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/487/06487123.pdf [firstpage_image] =>[orig_patent_app_number] => 09857451 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/857451
Semiconductor integrated circuit, ink cartridge having the semiconductor integrated circuit, and inkjet recording device having the ink cartridge attached Jul 31, 2001 Issued
Array ( [id] => 1578348 [patent_doc_number] => 06469942 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-22 [patent_title] => 'System for word line boosting' [patent_app_type] => B1 [patent_app_number] => 09/920248 [patent_app_country] => US [patent_app_date] => 2001-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1576 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/469/06469942.pdf [firstpage_image] =>[orig_patent_app_number] => 09920248 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/920248
System for word line boosting Jul 30, 2001 Issued
Array ( [id] => 6691715 [patent_doc_number] => 20030039147 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-27 [patent_title] => 'System for source side sensing' [patent_app_type] => new [patent_app_number] => 09/920249 [patent_app_country] => US [patent_app_date] => 2001-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1298 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0039/20030039147.pdf [firstpage_image] =>[orig_patent_app_number] => 09920249 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/920249
System for source side sensing Jul 30, 2001 Issued
Array ( [id] => 776033 [patent_doc_number] => 07002854 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-02-21 [patent_title] => 'Internal voltage level control circuit and semiconductor memory device as well as method of controlling the same' [patent_app_type] => utility [patent_app_number] => 10/343042 [patent_app_country] => US [patent_app_date] => 2001-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 21875 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/002/07002854.pdf [firstpage_image] =>[orig_patent_app_number] => 10343042 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/343042
Internal voltage level control circuit and semiconductor memory device as well as method of controlling the same Jul 23, 2001 Issued
Array ( [id] => 6030794 [patent_doc_number] => 20020018388 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-14 [patent_title] => 'Semiconductor device, method for refreshing the same, and electronic equipment' [patent_app_type] => new [patent_app_number] => 09/907755 [patent_app_country] => US [patent_app_date] => 2001-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7590 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0018/20020018388.pdf [firstpage_image] =>[orig_patent_app_number] => 09907755 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/907755
Semiconductor device, method for refreshing the same, and electronic equipment Jul 18, 2001 Issued
Array ( [id] => 1396528 [patent_doc_number] => 06548902 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-15 [patent_title] => 'Semiconductor integrated circuit device, circuit design apparatus, and circuit design method' [patent_app_type] => B2 [patent_app_number] => 09/907767 [patent_app_country] => US [patent_app_date] => 2001-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 8791 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/548/06548902.pdf [firstpage_image] =>[orig_patent_app_number] => 09907767 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/907767
Semiconductor integrated circuit device, circuit design apparatus, and circuit design method Jul 18, 2001 Issued
Array ( [id] => 1478487 [patent_doc_number] => 06388929 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-14 [patent_title] => 'Semiconductor memory device performing redundancy repair based on operation test and semiconductor integrated circuit device having the same' [patent_app_type] => B1 [patent_app_number] => 09/906654 [patent_app_country] => US [patent_app_date] => 2001-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 28 [patent_no_of_words] => 15238 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/388/06388929.pdf [firstpage_image] =>[orig_patent_app_number] => 09906654 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/906654
Semiconductor memory device performing redundancy repair based on operation test and semiconductor integrated circuit device having the same Jul 17, 2001 Issued
Array ( [id] => 1564332 [patent_doc_number] => 06438061 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-20 [patent_title] => 'Dynamic random access memory with low power consumption' [patent_app_type] => B1 [patent_app_number] => 09/907449 [patent_app_country] => US [patent_app_date] => 2001-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3583 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/438/06438061.pdf [firstpage_image] =>[orig_patent_app_number] => 09907449 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/907449
Dynamic random access memory with low power consumption Jul 17, 2001 Issued
Array ( [id] => 6590479 [patent_doc_number] => 20020015325 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-07 [patent_title] => 'Method for controlling re-writing operation for memory cell in semiconductor integrated circuit, semiconductor integrated circuit, semiconductor device equpped with many of the semiconductor integrated circuits, and electronic apparatus using the semiconductor device' [patent_app_type] => new [patent_app_number] => 09/904448 [patent_app_country] => US [patent_app_date] => 2001-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3606 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0015/20020015325.pdf [firstpage_image] =>[orig_patent_app_number] => 09904448 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/904448
METHOD FOR CONTROLLING RE-WRITING OPERATION FOR MEMORY CELL IN SEMICONDUCTOR INTEGRATED CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT, SEMICONDUCTOR DEVICE EQUIPPED WITH MANY OF THE SEMICONDUCTOR INTEGRATED CIRCUITS, AND ELECTRONIC APPARATUS USING THE SEMICONDUCTOR DEVICE Jul 11, 2001 Issued
Array ( [id] => 1421929 [patent_doc_number] => 06543035 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-01 [patent_title] => 'LCR extraction method and computer program for performing LCR extraction in LSI design process' [patent_app_type] => B2 [patent_app_number] => 09/901604 [patent_app_country] => US [patent_app_date] => 2001-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 4858 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/543/06543035.pdf [firstpage_image] =>[orig_patent_app_number] => 09901604 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/901604
LCR extraction method and computer program for performing LCR extraction in LSI design process Jul 10, 2001 Issued
Array ( [id] => 6335442 [patent_doc_number] => 20020033723 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-21 [patent_title] => 'Semiconductor memory device which controls sense amplifier for detecting bit line bridge and method of controlling the semiconductor memory device' [patent_app_type] => new [patent_app_number] => 09/901050 [patent_app_country] => US [patent_app_date] => 2001-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5428 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0033/20020033723.pdf [firstpage_image] =>[orig_patent_app_number] => 09901050 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/901050
Semiconductor memory device which controls sense amplifier for detecting bit line bridge and method of controlling the semiconductor memory device Jul 9, 2001 Issued
Array ( [id] => 1461084 [patent_doc_number] => 06426892 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-07-30 [patent_title] => 'Nonvolatile semiconductor memory device for storing multivalued data' [patent_app_type] => B2 [patent_app_number] => 09/898032 [patent_app_country] => US [patent_app_date] => 2001-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 31 [patent_no_of_words] => 13335 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/426/06426892.pdf [firstpage_image] =>[orig_patent_app_number] => 09898032 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/898032
Nonvolatile semiconductor memory device for storing multivalued data Jul 4, 2001 Issued
Array ( [id] => 6584433 [patent_doc_number] => 20020041509 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-11 [patent_title] => 'Circuit and method for on-board programming of prd serial EEPROMS' [patent_app_type] => new [patent_app_number] => 09/898512 [patent_app_country] => US [patent_app_date] => 2001-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2749 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0041/20020041509.pdf [firstpage_image] =>[orig_patent_app_number] => 09898512 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/898512
Apparatus for on-board programming of serial EEPROMS Jul 2, 2001 Issued
Array ( [id] => 6753903 [patent_doc_number] => 20030001679 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-02 [patent_title] => 'Sub-ranging wide-bandwidth low noise PLL architecture' [patent_app_type] => new [patent_app_number] => 09/896946 [patent_app_country] => US [patent_app_date] => 2001-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2836 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 18 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20030001679.pdf [firstpage_image] =>[orig_patent_app_number] => 09896946 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/896946
Selective adjustment of voltage controlled oscillator gain in a phase-locked loop Jul 1, 2001 Issued
Array ( [id] => 6884400 [patent_doc_number] => 20010038559 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-08 [patent_title] => 'Device and method for margin testing a semiconductor memory by applying a stressing voltage simultaneously to complementary and true digit lines' [patent_app_type] => new [patent_app_number] => 09/897360 [patent_app_country] => US [patent_app_date] => 2001-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3143 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20010038559.pdf [firstpage_image] =>[orig_patent_app_number] => 09897360 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/897360
Device and method for margin testing a semiconductor memory by applying a stressing voltage simultaneously to complementary and true digit lines Jul 1, 2001 Issued
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