Search

Son Luu Mai

Examiner (ID: 18155, Phone: (571)272-1786 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2511, 2827, 2818
Total Applications
3063
Issued Applications
2917
Pending Applications
45
Abandoned Applications
107

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1411858 [patent_doc_number] => 06532187 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-03-11 [patent_title] => 'Semiconductor device having integrated memory and logic' [patent_app_type] => B2 [patent_app_number] => 09/867547 [patent_app_country] => US [patent_app_date] => 2001-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 14665 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/532/06532187.pdf [firstpage_image] =>[orig_patent_app_number] => 09867547 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/867547
Semiconductor device having integrated memory and logic May 30, 2001 Issued
Array ( [id] => 1297481 [patent_doc_number] => 06634017 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-10-14 [patent_title] => 'System LSI development apparatus and the method thereof for developing a system optimal to an application' [patent_app_type] => B2 [patent_app_number] => 09/865289 [patent_app_country] => US [patent_app_date] => 2001-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 31 [patent_no_of_words] => 12665 [patent_no_of_claims] => 140 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/634/06634017.pdf [firstpage_image] =>[orig_patent_app_number] => 09865289 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/865289
System LSI development apparatus and the method thereof for developing a system optimal to an application May 28, 2001 Issued
Array ( [id] => 6882149 [patent_doc_number] => 20010048621 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-06 [patent_title] => 'Method for testing a multiplicity of word lines of a semiconductor memory configuration' [patent_app_type] => new [patent_app_number] => 09/867254 [patent_app_country] => US [patent_app_date] => 2001-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1585 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0048/20010048621.pdf [firstpage_image] =>[orig_patent_app_number] => 09867254 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/867254
Method for testing a multiplicity of word lines of a semiconductor memory configuration May 28, 2001 Issued
Array ( [id] => 1454374 [patent_doc_number] => 06456537 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-24 [patent_title] => 'Techniques for erasing an erasable programmable read only memory (EPROM) cell' [patent_app_type] => B1 [patent_app_number] => 09/870050 [patent_app_country] => US [patent_app_date] => 2001-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3516 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/456/06456537.pdf [firstpage_image] =>[orig_patent_app_number] => 09870050 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/870050
Techniques for erasing an erasable programmable read only memory (EPROM) cell May 28, 2001 Issued
Array ( [id] => 895231 [patent_doc_number] => RE040132 [patent_country] => US [patent_kind] => E1 [patent_issue_date] => 2008-03-04 [patent_title] => 'Large scale integrated circuit with sense amplifier circuits for low voltage operation' [patent_app_type] => reissue [patent_app_number] => 09/864338 [patent_app_country] => US [patent_app_date] => 2001-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 129 [patent_figures_cnt] => 182 [patent_no_of_words] => 59089 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/040/RE040132.pdf [firstpage_image] =>[orig_patent_app_number] => 09864338 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/864338
Large scale integrated circuit with sense amplifier circuits for low voltage operation May 24, 2001 Issued
Array ( [id] => 1433789 [patent_doc_number] => 06341079 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-22 [patent_title] => 'Content addressable memory device' [patent_app_type] => B1 [patent_app_number] => 09/863848 [patent_app_country] => US [patent_app_date] => 2001-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 6010 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/341/06341079.pdf [firstpage_image] =>[orig_patent_app_number] => 09863848 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/863848
Content addressable memory device May 22, 2001 Issued
Array ( [id] => 6933876 [patent_doc_number] => 20010055220 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-27 [patent_title] => 'Voltage regulation device for reference cell of a dynamic random access memory, reference cell, memory and associated process' [patent_app_type] => new [patent_app_number] => 09/853254 [patent_app_country] => US [patent_app_date] => 2001-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2681 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 17 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20010055220.pdf [firstpage_image] =>[orig_patent_app_number] => 09853254 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/853254
Voltage regulation device for reference cell of a dynamic random access memory, reference cell, memory and associated process May 10, 2001 Abandoned
Array ( [id] => 1443069 [patent_doc_number] => 06335904 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-01 [patent_title] => 'Semiconductor memory system, and access control method for semiconductor memory and semiconductor memory' [patent_app_type] => B1 [patent_app_number] => 09/852037 [patent_app_country] => US [patent_app_date] => 2001-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 8571 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/335/06335904.pdf [firstpage_image] =>[orig_patent_app_number] => 09852037 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/852037
Semiconductor memory system, and access control method for semiconductor memory and semiconductor memory May 9, 2001 Issued
Array ( [id] => 1555132 [patent_doc_number] => 06400619 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-04 [patent_title] => 'Micro-cell redundancy scheme for high performance eDRAM' [patent_app_type] => B1 [patent_app_number] => 09/841950 [patent_app_country] => US [patent_app_date] => 2001-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3844 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/400/06400619.pdf [firstpage_image] =>[orig_patent_app_number] => 09841950 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/841950
Micro-cell redundancy scheme for high performance eDRAM Apr 24, 2001 Issued
Array ( [id] => 7630496 [patent_doc_number] => 06636440 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-10-21 [patent_title] => 'Method for operation of an EEPROM array, including refresh thereof' [patent_app_type] => B2 [patent_app_number] => 09/841052 [patent_app_country] => US [patent_app_date] => 2001-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 6299 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 13 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/636/06636440.pdf [firstpage_image] =>[orig_patent_app_number] => 09841052 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/841052
Method for operation of an EEPROM array, including refresh thereof Apr 24, 2001 Issued
Array ( [id] => 1603856 [patent_doc_number] => 06434039 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'Circuit configuration for reading a memory cell having a ferroelectric capacitor' [patent_app_type] => B1 [patent_app_number] => 09/838750 [patent_app_country] => US [patent_app_date] => 2001-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 2892 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/434/06434039.pdf [firstpage_image] =>[orig_patent_app_number] => 09838750 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/838750
Circuit configuration for reading a memory cell having a ferroelectric capacitor Apr 18, 2001 Issued
Array ( [id] => 1450012 [patent_doc_number] => 06370060 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-04-09 [patent_title] => 'Semiconductor memory device' [patent_app_type] => B2 [patent_app_number] => 09/836949 [patent_app_country] => US [patent_app_date] => 2001-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 10787 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/370/06370060.pdf [firstpage_image] =>[orig_patent_app_number] => 09836949 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/836949
Semiconductor memory device Apr 16, 2001 Issued
Array ( [id] => 1509164 [patent_doc_number] => 06467066 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-10-15 [patent_title] => 'Semiconductor device simulation method, semiconductor device simulator, computer program for semiconductor device simulation, and method of manufacturing the semiconductor device' [patent_app_type] => B2 [patent_app_number] => 09/833761 [patent_app_country] => US [patent_app_date] => 2001-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 5294 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/467/06467066.pdf [firstpage_image] =>[orig_patent_app_number] => 09833761 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/833761
Semiconductor device simulation method, semiconductor device simulator, computer program for semiconductor device simulation, and method of manufacturing the semiconductor device Apr 12, 2001 Issued
Array ( [id] => 5934674 [patent_doc_number] => 20020060945 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-23 [patent_title] => 'SYNCHRONOUS SEMICONDUCTOR DEVICE AND METHOD FOR LATCHING INPUT SIGNALS' [patent_app_type] => new [patent_app_number] => 09/832851 [patent_app_country] => US [patent_app_date] => 2001-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6967 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0060/20020060945.pdf [firstpage_image] =>[orig_patent_app_number] => 09832851 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/832851
Synchronous semiconductor device and method for latching input signals Apr 11, 2001 Issued
Array ( [id] => 6884405 [patent_doc_number] => 20010038564 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-08 [patent_title] => 'Sense amplifier' [patent_app_type] => new [patent_app_number] => 09/833052 [patent_app_country] => US [patent_app_date] => 2001-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 6249 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20010038564.pdf [firstpage_image] =>[orig_patent_app_number] => 09833052 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/833052
Sense amplifier Apr 10, 2001 Issued
Array ( [id] => 1341917 [patent_doc_number] => 06597594 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-07-22 [patent_title] => 'Content addressable memory cells and systems and devices using the same' [patent_app_type] => B2 [patent_app_number] => 09/832391 [patent_app_country] => US [patent_app_date] => 2001-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 6461 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/597/06597594.pdf [firstpage_image] =>[orig_patent_app_number] => 09832391 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/832391
Content addressable memory cells and systems and devices using the same Apr 9, 2001 Issued
Array ( [id] => 736670 [patent_doc_number] => 07038925 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-05-02 [patent_title] => 'Static semiconductor memory device having T-type bit line structure' [patent_app_type] => utility [patent_app_number] => 09/829046 [patent_app_country] => US [patent_app_date] => 2001-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 10485 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 520 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/038/07038925.pdf [firstpage_image] =>[orig_patent_app_number] => 09829046 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/829046
Static semiconductor memory device having T-type bit line structure Apr 9, 2001 Issued
Array ( [id] => 6094391 [patent_doc_number] => 20020051401 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-02 [patent_title] => 'SEMICONDUCTOR MEMORY ARCHITECTURE FOR MINIMIZING INPUT/OUTPUT DATA PATHS' [patent_app_type] => new [patent_app_number] => 09/829650 [patent_app_country] => US [patent_app_date] => 2001-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3665 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0051/20020051401.pdf [firstpage_image] =>[orig_patent_app_number] => 09829650 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/829650
Semiconductor memory architecture for minimizing input/output data paths Apr 9, 2001 Issued
Array ( [id] => 1555166 [patent_doc_number] => 06400632 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-04 [patent_title] => 'Semiconductor device including a fuse circuit in which the electric current is cut off after blowing so as to prevent voltage fall' [patent_app_type] => B1 [patent_app_number] => 09/820853 [patent_app_country] => US [patent_app_date] => 2001-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 36 [patent_no_of_words] => 12847 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/400/06400632.pdf [firstpage_image] =>[orig_patent_app_number] => 09820853 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/820853
Semiconductor device including a fuse circuit in which the electric current is cut off after blowing so as to prevent voltage fall Mar 29, 2001 Issued
Array ( [id] => 6061960 [patent_doc_number] => 20020031009 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-14 [patent_title] => 'Semiconductor memory device having source areas of memory cells supplied with a common voltage' [patent_app_type] => new [patent_app_number] => 09/818652 [patent_app_country] => US [patent_app_date] => 2001-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5708 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0031/20020031009.pdf [firstpage_image] =>[orig_patent_app_number] => 09818652 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/818652
Semiconductor memory device having source areas of memory cells supplied with a common voltage Mar 27, 2001 Issued
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