
Son Luu Mai
Examiner (ID: 18155, Phone: (571)272-1786 , Office: P/2827 )
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2511, 2827, 2818 |
| Total Applications | 3063 |
| Issued Applications | 2917 |
| Pending Applications | 45 |
| Abandoned Applications | 107 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1599727
[patent_doc_number] => 06385105
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2002-05-07
[patent_title] => 'Semiconductor memory and method of saving energy of the memory'
[patent_app_type] => B2
[patent_app_number] => 09/819352
[patent_app_country] => US
[patent_app_date] => 2001-03-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 1520
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/385/06385105.pdf
[firstpage_image] =>[orig_patent_app_number] => 09819352
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/819352 | Semiconductor memory and method of saving energy of the memory | Mar 27, 2001 | Issued |
Array
(
[id] => 1585361
[patent_doc_number] => 06424572
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-07-23
[patent_title] => 'Semiconductor memory apparatus that can surely attain discharge operation while reducing discharge period when reading operation is done'
[patent_app_type] => B1
[patent_app_number] => 09/817049
[patent_app_country] => US
[patent_app_date] => 2001-03-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 27
[patent_no_of_words] => 8862
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/424/06424572.pdf
[firstpage_image] =>[orig_patent_app_number] => 09817049
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/817049 | Semiconductor memory apparatus that can surely attain discharge operation while reducing discharge period when reading operation is done | Mar 26, 2001 | Issued |
Array
(
[id] => 5842232
[patent_doc_number] => 20020131290
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-09-19
[patent_title] => 'Device and method to reduce wordline RC time constant in semiconductor memory devices'
[patent_app_type] => new
[patent_app_number] => 09/808750
[patent_app_country] => US
[patent_app_date] => 2001-03-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3683
[patent_no_of_claims] => 54
[patent_no_of_ind_claims] => 11
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0131/20020131290.pdf
[firstpage_image] =>[orig_patent_app_number] => 09808750
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/808750 | Device and method to reduce wordline RC time constant in semiconductor memory devices | Mar 14, 2001 | Issued |
Array
(
[id] => 1431680
[patent_doc_number] => 06504756
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-01-07
[patent_title] => 'Dual floating gate programmable read only memory cell structure and method for its fabrication and operation'
[patent_app_type] => B2
[patent_app_number] => 09/808158
[patent_app_country] => US
[patent_app_date] => 2001-03-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 50
[patent_no_of_words] => 6625
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 194
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/504/06504756.pdf
[firstpage_image] =>[orig_patent_app_number] => 09808158
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/808158 | Dual floating gate programmable read only memory cell structure and method for its fabrication and operation | Mar 14, 2001 | Issued |
Array
(
[id] => 1517679
[patent_doc_number] => 06421282
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-07-16
[patent_title] => 'Cascade-booted programming voltage circuit'
[patent_app_type] => B1
[patent_app_number] => 09/808249
[patent_app_country] => US
[patent_app_date] => 2001-03-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5475
[patent_no_of_claims] => 33
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 69
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/421/06421282.pdf
[firstpage_image] =>[orig_patent_app_number] => 09808249
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/808249 | Cascade-booted programming voltage circuit | Mar 13, 2001 | Issued |
Array
(
[id] => 1564173
[patent_doc_number] => 06438014
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2002-08-20
[patent_title] => 'High speed access compatible memory module'
[patent_app_type] => B2
[patent_app_number] => 09/803148
[patent_app_country] => US
[patent_app_date] => 2001-03-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 31
[patent_figures_cnt] => 62
[patent_no_of_words] => 13566
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/438/06438014.pdf
[firstpage_image] =>[orig_patent_app_number] => 09803148
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/803148 | High speed access compatible memory module | Mar 11, 2001 | Issued |
Array
(
[id] => 1565145
[patent_doc_number] => 06363005
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-03-26
[patent_title] => 'Method of increasing operating speed of SRAM'
[patent_app_type] => B1
[patent_app_number] => 09/801349
[patent_app_country] => US
[patent_app_date] => 2001-03-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 1766
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/363/06363005.pdf
[firstpage_image] =>[orig_patent_app_number] => 09801349
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/801349 | Method of increasing operating speed of SRAM | Mar 6, 2001 | Issued |
Array
(
[id] => 1480085
[patent_doc_number] => 06344994
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-02-05
[patent_title] => 'Data retention characteristics as a result of high temperature bake'
[patent_app_type] => B1
[patent_app_number] => 09/795849
[patent_app_country] => US
[patent_app_date] => 2001-02-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 22
[patent_no_of_words] => 13597
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 69
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/344/06344994.pdf
[firstpage_image] =>[orig_patent_app_number] => 09795849
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/795849 | Data retention characteristics as a result of high temperature bake | Feb 27, 2001 | Issued |
Array
(
[id] => 1511367
[patent_doc_number] => 06442074
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-08-27
[patent_title] => 'Tailored erase method using higher program VT and higher negative gate erase'
[patent_app_type] => B1
[patent_app_number] => 09/795854
[patent_app_country] => US
[patent_app_date] => 2001-02-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 22
[patent_no_of_words] => 13581
[patent_no_of_claims] => 56
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/442/06442074.pdf
[firstpage_image] =>[orig_patent_app_number] => 09795854
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/795854 | Tailored erase method using higher program VT and higher negative gate erase | Feb 27, 2001 | Issued |
Array
(
[id] => 6907882
[patent_doc_number] => 20010010649
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-08-02
[patent_title] => 'Novel flash memory using micro vacuum tube technology'
[patent_app_type] => new
[patent_app_number] => 09/784820
[patent_app_country] => US
[patent_app_date] => 2001-02-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4682
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 44
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0010/20010010649.pdf
[firstpage_image] =>[orig_patent_app_number] => 09784820
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/784820 | Flash memory using micro vacuum tube technology | Feb 19, 2001 | Issued |
Array
(
[id] => 6891641
[patent_doc_number] => 20010017803
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-08-30
[patent_title] => 'Semiconductor memory'
[patent_app_type] => new
[patent_app_number] => 09/781054
[patent_app_country] => US
[patent_app_date] => 2001-02-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 7816
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 64
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0017/20010017803.pdf
[firstpage_image] =>[orig_patent_app_number] => 09781054
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/781054 | Semiconductor memory having parallel test mode | Feb 7, 2001 | Issued |
Array
(
[id] => 1454350
[patent_doc_number] => 06456532
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-09-24
[patent_title] => 'Semiconductor memory device'
[patent_app_type] => B1
[patent_app_number] => 09/673546
[patent_app_country] => US
[patent_app_date] => 2001-02-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 7474
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 156
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/456/06456532.pdf
[firstpage_image] =>[orig_patent_app_number] => 09673546
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/673546 | Semiconductor memory device | Feb 6, 2001 | Issued |
Array
(
[id] => 6893548
[patent_doc_number] => 20010015914
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-08-23
[patent_title] => 'Integrated semiconductor memory'
[patent_app_type] => new
[patent_app_number] => 09/776950
[patent_app_country] => US
[patent_app_date] => 2001-02-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4547
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0015/20010015914.pdf
[firstpage_image] =>[orig_patent_app_number] => 09776950
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/776950 | Integrated semiconductor memory | Feb 4, 2001 | Issued |
Array
(
[id] => 6466618
[patent_doc_number] => 20020021593
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-02-21
[patent_title] => 'Semiconductor memory device with a redundancy structure'
[patent_app_type] => new
[patent_app_number] => 09/768352
[patent_app_country] => US
[patent_app_date] => 2001-01-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 28
[patent_figures_cnt] => 28
[patent_no_of_words] => 8394
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 132
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0021/20020021593.pdf
[firstpage_image] =>[orig_patent_app_number] => 09768352
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/768352 | Semiconductor memory device with a redundancy structure | Jan 24, 2001 | Abandoned |
Array
(
[id] => 6878023
[patent_doc_number] => 20010002178
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-05-31
[patent_title] => 'Destructive read type memory circuit, restoring circuit for the same and sense amplifier'
[patent_app_type] => new-utility
[patent_app_number] => 09/768465
[patent_app_country] => US
[patent_app_date] => 2001-01-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 34
[patent_figures_cnt] => 34
[patent_no_of_words] => 20967
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 11
[patent_words_short_claim] => 75
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0002/20010002178.pdf
[firstpage_image] =>[orig_patent_app_number] => 09768465
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/768465 | Destructive read type memory circuit, restoring circuit for the same and sense amplifier | Jan 24, 2001 | Issued |
Array
(
[id] => 1450021
[patent_doc_number] => 06370063
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2002-04-09
[patent_title] => 'Word line driver having a divided bias line in a non-volatile memory device and method for driving word lines'
[patent_app_type] => B2
[patent_app_number] => 09/768649
[patent_app_country] => US
[patent_app_date] => 2001-01-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 3867
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/370/06370063.pdf
[firstpage_image] =>[orig_patent_app_number] => 09768649
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/768649 | Word line driver having a divided bias line in a non-volatile memory device and method for driving word lines | Jan 23, 2001 | Issued |
Array
(
[id] => 6899852
[patent_doc_number] => 20010009528
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-07-26
[patent_title] => 'Method for storing a temperature threshold in an integrated circuit, method for storing a temperature threshold in a dynaic random access memory, method of modifying dynamic random access memory operation in response to temperature, programmable temperature sensing circuit and memory integrated circuit'
[patent_app_type] => new
[patent_app_number] => 09/768897
[patent_app_country] => US
[patent_app_date] => 2001-01-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 5162
[patent_no_of_claims] => 40
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 33
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0009/20010009528.pdf
[firstpage_image] =>[orig_patent_app_number] => 09768897
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/768897 | METHOD FOR STORING A TEMPERATURE THRESHOLD IN AN INTEGRATED CIRCUIT, METHOD FOR STORING A TEMPERATURE THRESHOLD IN A DYNAMIC RANDOM ACCESS MEMORY, METHOD OF MODIFYING DYNAMIC RANDOM ACCESS MEMORY OPERATION IN RESPONSE TO TEMPERATURE, PROGRAMMABLE TEMPERATURE SENSING CIRCUIT AND MEMORY INTEGRATED CIRCUIT | Jan 22, 2001 | Issued |
Array
(
[id] => 1322817
[patent_doc_number] => 06608793
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-08-19
[patent_title] => 'Efficient management method of memory cell array'
[patent_app_type] => B2
[patent_app_number] => 09/765652
[patent_app_country] => US
[patent_app_date] => 2001-01-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 3944
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/608/06608793.pdf
[firstpage_image] =>[orig_patent_app_number] => 09765652
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/765652 | Efficient management method of memory cell array | Jan 21, 2001 | Issued |
Array
(
[id] => 6878024
[patent_doc_number] => 20010002179
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-05-31
[patent_title] => 'LSI device with memory and logics mounted thereon'
[patent_app_type] => new-utility
[patent_app_number] => 09/764446
[patent_app_country] => US
[patent_app_date] => 2001-01-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 25
[patent_no_of_words] => 11139
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0002/20010002179.pdf
[firstpage_image] =>[orig_patent_app_number] => 09764446
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/764446 | LSI device with memory and logics mounted thereon | Jan 18, 2001 | Issued |
Array
(
[id] => 1493416
[patent_doc_number] => 06418068
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-07-09
[patent_title] => 'Self-healing memory'
[patent_app_type] => B1
[patent_app_number] => 09/766354
[patent_app_country] => US
[patent_app_date] => 2001-01-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 11
[patent_no_of_words] => 7778
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/418/06418068.pdf
[firstpage_image] =>[orig_patent_app_number] => 09766354
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/766354 | Self-healing memory | Jan 18, 2001 | Issued |