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Son Luu Mai

Examiner (ID: 18155)

Most Active Art Unit
2827
Art Unit(s)
2511, 2827, 2818
Total Applications
3063
Issued Applications
2917
Pending Applications
45
Abandoned Applications
107

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6947493 [patent_doc_number] => 20010021127 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-09-13 [patent_title] => 'Semiconductor memory capable of detecting defective data in the memory cells thereof' [patent_app_type] => new [patent_app_number] => 09/761148 [patent_app_country] => US [patent_app_date] => 2001-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 12708 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0021/20010021127.pdf [firstpage_image] =>[orig_patent_app_number] => 09761148 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/761148
Semiconductor memory capable of detecting defective data in the memory cells thereof Jan 16, 2001 Issued
Array ( [id] => 1433807 [patent_doc_number] => 06341097 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-22 [patent_title] => 'Selective address space refresh mode' [patent_app_type] => B1 [patent_app_number] => 09/764654 [patent_app_country] => US [patent_app_date] => 2001-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1454 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/341/06341097.pdf [firstpage_image] =>[orig_patent_app_number] => 09764654 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/764654
Selective address space refresh mode Jan 16, 2001 Issued
Array ( [id] => 4344770 [patent_doc_number] => 06314028 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-06 [patent_title] => 'Semiconductor memory device capable of stable sensing operation' [patent_app_type] => 1 [patent_app_number] => 9/755246 [patent_app_country] => US [patent_app_date] => 2001-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 40 [patent_no_of_words] => 23103 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/314/06314028.pdf [firstpage_image] =>[orig_patent_app_number] => 755246 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/755246
Semiconductor memory device capable of stable sensing operation Jan 7, 2001 Issued
Array ( [id] => 6139708 [patent_doc_number] => 20020001235 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-03 [patent_title] => 'Semiconductor memory device allowing effective detection of leak failure' [patent_app_type] => new [patent_app_number] => 09/753452 [patent_app_country] => US [patent_app_date] => 2001-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6134 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20020001235.pdf [firstpage_image] =>[orig_patent_app_number] => 09753452 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/753452
Semiconductor memory device allowing effective detection of leak failure Jan 3, 2001 Issued
Array ( [id] => 6597016 [patent_doc_number] => 20020085422 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-04 [patent_title] => 'Drain bias for non-volatile memory' [patent_app_type] => new [patent_app_number] => 09/752550 [patent_app_country] => US [patent_app_date] => 2000-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3429 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20020085422.pdf [firstpage_image] =>[orig_patent_app_number] => 09752550 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/752550
Kicker for non-volatile memory drain bias Dec 28, 2000 Issued
Array ( [id] => 1603866 [patent_doc_number] => 06434049 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'Sample and hold voltage reference source' [patent_app_type] => B1 [patent_app_number] => 09/753354 [patent_app_country] => US [patent_app_date] => 2000-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3396 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/434/06434049.pdf [firstpage_image] =>[orig_patent_app_number] => 09753354 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/753354
Sample and hold voltage reference source Dec 28, 2000 Issued
Array ( [id] => 6907884 [patent_doc_number] => 20010010651 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-02 [patent_title] => 'Semiconductor integrated circuit' [patent_app_type] => new [patent_app_number] => 09/750352 [patent_app_country] => US [patent_app_date] => 2000-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 9894 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0010/20010010651.pdf [firstpage_image] =>[orig_patent_app_number] => 09750352 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/750352
Semiconductor integrated circuit Dec 28, 2000 Issued
Array ( [id] => 1525626 [patent_doc_number] => 06353558 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-05 [patent_title] => 'Method and apparatus for writing to memory cells' [patent_app_type] => B1 [patent_app_number] => 09/750254 [patent_app_country] => US [patent_app_date] => 2000-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5257 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/353/06353558.pdf [firstpage_image] =>[orig_patent_app_number] => 09750254 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/750254
Method and apparatus for writing to memory cells Dec 27, 2000 Issued
Array ( [id] => 6999316 [patent_doc_number] => 20010053097 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-20 [patent_title] => 'Voltage detecting circuit for semiconductor memory device' [patent_app_type] => new [patent_app_number] => 09/748350 [patent_app_country] => US [patent_app_date] => 2000-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3906 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0053/20010053097.pdf [firstpage_image] =>[orig_patent_app_number] => 09748350 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/748350
Voltage detecting circuit for semiconductor memory device Dec 21, 2000 Issued
Array ( [id] => 1437666 [patent_doc_number] => 06356478 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-12 [patent_title] => 'Flash based control for field programmable gate array' [patent_app_type] => B1 [patent_app_number] => 09/748648 [patent_app_country] => US [patent_app_date] => 2000-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3290 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/356/06356478.pdf [firstpage_image] =>[orig_patent_app_number] => 09748648 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/748648
Flash based control for field programmable gate array Dec 20, 2000 Issued
Array ( [id] => 6126559 [patent_doc_number] => 20020075744 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-20 [patent_title] => 'Antifuse memory cell and antifuse memory cell array' [patent_app_type] => new [patent_app_number] => 09/742550 [patent_app_country] => US [patent_app_date] => 2000-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3361 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0075/20020075744.pdf [firstpage_image] =>[orig_patent_app_number] => 09742550 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/742550
Antifuse memory cell and antifuse memory cell array Dec 19, 2000 Issued
Array ( [id] => 6888929 [patent_doc_number] => 20010024384 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-09-27 [patent_title] => 'Semiconductor memory device capable of reliably performing burn-in test at wafer level' [patent_app_type] => new [patent_app_number] => 09/739350 [patent_app_country] => US [patent_app_date] => 2000-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11429 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0024/20010024384.pdf [firstpage_image] =>[orig_patent_app_number] => 09739350 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/739350
Semiconductor memory device capable of reliably performing burn-in test at wafer level Dec 18, 2000 Issued
Array ( [id] => 7039988 [patent_doc_number] => 20010005011 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-06-28 [patent_title] => 'Magnetic tunnel junction device, magnetic memory adopting the same, magnetic memory cell and access method of the same' [patent_app_type] => new-utility [patent_app_number] => 09/733646 [patent_app_country] => US [patent_app_date] => 2000-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9901 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20010005011.pdf [firstpage_image] =>[orig_patent_app_number] => 09733646 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/733646
Magnetic tunnel junction device, magnetic memory adopting the same, magnetic memory cell and access method of the same Dec 7, 2000 Issued
Array ( [id] => 7040530 [patent_doc_number] => 20010005330 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-06-28 [patent_title] => 'Nand-type flash memory device and method of operating the same' [patent_app_type] => new-utility [patent_app_number] => 09/733255 [patent_app_country] => US [patent_app_date] => 2000-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10827 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20010005330.pdf [firstpage_image] =>[orig_patent_app_number] => 09733255 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/733255
NAND-type flash memory device and method of operating the same Dec 7, 2000 Issued
Array ( [id] => 6875389 [patent_doc_number] => 20010000133 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-04-05 [patent_title] => 'Semiconductor integrated circuit device and method of activating the same' [patent_app_type] => new-utility [patent_app_number] => 09/729273 [patent_app_country] => US [patent_app_date] => 2000-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 20650 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0000/20010000133.pdf [firstpage_image] =>[orig_patent_app_number] => 09729273 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/729273
Semiconductor integrated circuit device and method of activating the same Dec 4, 2000 Issued
Array ( [id] => 1488609 [patent_doc_number] => 06366512 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-02 [patent_title] => 'Error write protection circuit used in semiconductor memory device' [patent_app_type] => B1 [patent_app_number] => 09/726255 [patent_app_country] => US [patent_app_date] => 2000-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2466 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/366/06366512.pdf [firstpage_image] =>[orig_patent_app_number] => 09726255 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/726255
Error write protection circuit used in semiconductor memory device Nov 29, 2000 Issued
Array ( [id] => 6878021 [patent_doc_number] => 20010002176 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-05-31 [patent_title] => 'Semiconductor memory device having a large band width and allowing efficient execution of redundant repair' [patent_app_type] => new-utility [patent_app_number] => 09/725020 [patent_app_country] => US [patent_app_date] => 2000-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 17368 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 284 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20010002176.pdf [firstpage_image] =>[orig_patent_app_number] => 09725020 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/725020
Semiconductor memory device having a large band width and allowing efficient execution of redundant repair Nov 28, 2000 Issued
Array ( [id] => 1437668 [patent_doc_number] => 06356479 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-12 [patent_title] => 'Semiconductor memory system' [patent_app_type] => B1 [patent_app_number] => 09/722453 [patent_app_country] => US [patent_app_date] => 2000-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 13004 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/356/06356479.pdf [firstpage_image] =>[orig_patent_app_number] => 09722453 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/722453
Semiconductor memory system Nov 27, 2000 Issued
Array ( [id] => 1493357 [patent_doc_number] => 06418057 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-09 [patent_title] => 'Nonvolatile semiconductor memory device capable of correctly performing erasure/programming completion determination even in presence of defective bit' [patent_app_type] => B1 [patent_app_number] => 09/717248 [patent_app_country] => US [patent_app_date] => 2000-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 22 [patent_no_of_words] => 16284 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/418/06418057.pdf [firstpage_image] =>[orig_patent_app_number] => 09717248 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/717248
Nonvolatile semiconductor memory device capable of correctly performing erasure/programming completion determination even in presence of defective bit Nov 21, 2000 Issued
Array ( [id] => 4329610 [patent_doc_number] => 06331951 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-18 [patent_title] => 'Method and system for embedded chip erase verification' [patent_app_type] => 1 [patent_app_number] => 9/717550 [patent_app_country] => US [patent_app_date] => 2000-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8256 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/331/06331951.pdf [firstpage_image] =>[orig_patent_app_number] => 717550 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/717550
Method and system for embedded chip erase verification Nov 20, 2000 Issued
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