Search

Son Luu Mai

Examiner (ID: 18155, Phone: (571)272-1786 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2511, 2827, 2818
Total Applications
3063
Issued Applications
2917
Pending Applications
45
Abandoned Applications
107

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4418975 [patent_doc_number] => 06301141 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-09 [patent_title] => 'Die architecture accommodating high-speed semiconductor devices' [patent_app_type] => 1 [patent_app_number] => 9/652578 [patent_app_country] => US [patent_app_date] => 2000-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3243 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/301/06301141.pdf [firstpage_image] =>[orig_patent_app_number] => 652578 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/652578
Die architecture accommodating high-speed semiconductor devices Aug 30, 2000 Issued
Array ( [id] => 4317455 [patent_doc_number] => 06327167 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-04 [patent_title] => 'Die architecture accommodating high-speed semiconductor devices' [patent_app_type] => 1 [patent_app_number] => 9/652996 [patent_app_country] => US [patent_app_date] => 2000-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3242 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/327/06327167.pdf [firstpage_image] =>[orig_patent_app_number] => 652996 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/652996
Die architecture accommodating high-speed semiconductor devices Aug 30, 2000 Issued
Array ( [id] => 4419907 [patent_doc_number] => 06266266 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'Integrated circuit design exhibiting reduced capacitance' [patent_app_type] => 1 [patent_app_number] => 9/652824 [patent_app_country] => US [patent_app_date] => 2000-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 24 [patent_no_of_words] => 9985 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/266/06266266.pdf [firstpage_image] =>[orig_patent_app_number] => 652824 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/652824
Integrated circuit design exhibiting reduced capacitance Aug 30, 2000 Issued
Array ( [id] => 1564162 [patent_doc_number] => 06438011 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-20 [patent_title] => 'Die architecture accommodating high-speed semiconductor devices' [patent_app_type] => B1 [patent_app_number] => 09/652584 [patent_app_country] => US [patent_app_date] => 2000-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3360 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/438/06438011.pdf [firstpage_image] =>[orig_patent_app_number] => 09652584 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/652584
Die architecture accommodating high-speed semiconductor devices Aug 30, 2000 Issued
Array ( [id] => 4291109 [patent_doc_number] => 06282132 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Data-strobe input buffers for high-frequency SDRAMS' [patent_app_type] => 1 [patent_app_number] => 9/650550 [patent_app_country] => US [patent_app_date] => 2000-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4325 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/282/06282132.pdf [firstpage_image] =>[orig_patent_app_number] => 650550 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/650550
Data-strobe input buffers for high-frequency SDRAMS Aug 29, 2000 Issued
09/650546 SEMICONDUCTOR MEMORY HAVING DUAL PORT CELL SUPPORTING HIDDEN REFRESH Aug 29, 2000 Abandoned
Array ( [id] => 4271084 [patent_doc_number] => 06323088 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-27 [patent_title] => 'Dual floating gate programmable read only memory cell structure and method for its fabrication an operation' [patent_app_type] => 1 [patent_app_number] => 9/650078 [patent_app_country] => US [patent_app_date] => 2000-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 50 [patent_no_of_words] => 6541 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/323/06323088.pdf [firstpage_image] =>[orig_patent_app_number] => 650078 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/650078
Dual floating gate programmable read only memory cell structure and method for its fabrication an operation Aug 28, 2000 Issued
Array ( [id] => 4346404 [patent_doc_number] => 06333889 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-25 [patent_title] => 'Logic-merged semiconductor memory having high internal data transfer rate' [patent_app_type] => 1 [patent_app_number] => 9/645352 [patent_app_country] => US [patent_app_date] => 2000-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 35 [patent_no_of_words] => 18487 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/333/06333889.pdf [firstpage_image] =>[orig_patent_app_number] => 645352 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/645352
Logic-merged semiconductor memory having high internal data transfer rate Aug 24, 2000 Issued
Array ( [id] => 4393207 [patent_doc_number] => 06304488 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-16 [patent_title] => 'Current limiting negative switch circuit' [patent_app_type] => 1 [patent_app_number] => 9/649448 [patent_app_country] => US [patent_app_date] => 2000-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10575 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/304/06304488.pdf [firstpage_image] =>[orig_patent_app_number] => 649448 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/649448
Current limiting negative switch circuit Aug 24, 2000 Issued
Array ( [id] => 4418996 [patent_doc_number] => 06301143 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-09 [patent_title] => 'Semiconductor memory device with chip layout for enabling high speed operation' [patent_app_type] => 1 [patent_app_number] => 9/645552 [patent_app_country] => US [patent_app_date] => 2000-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 20 [patent_no_of_words] => 5163 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/301/06301143.pdf [firstpage_image] =>[orig_patent_app_number] => 645552 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/645552
Semiconductor memory device with chip layout for enabling high speed operation Aug 24, 2000 Issued
Array ( [id] => 4395487 [patent_doc_number] => 06278653 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'Reduced skew timing scheme for write circuitry used in memory circuits' [patent_app_type] => 1 [patent_app_number] => 9/644928 [patent_app_country] => US [patent_app_date] => 2000-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 7698 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/278/06278653.pdf [firstpage_image] =>[orig_patent_app_number] => 644928 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/644928
Reduced skew timing scheme for write circuitry used in memory circuits Aug 22, 2000 Issued
Array ( [id] => 1488585 [patent_doc_number] => 06366505 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-02 [patent_title] => 'Device for controlling a translator-type high voltage selector switch' [patent_app_type] => B1 [patent_app_number] => 09/628149 [patent_app_country] => US [patent_app_date] => 2000-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5109 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/366/06366505.pdf [firstpage_image] =>[orig_patent_app_number] => 09628149 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/628149
Device for controlling a translator-type high voltage selector switch Jul 27, 2000 Issued
Array ( [id] => 4273646 [patent_doc_number] => 06259652 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Synchronous integrated memory' [patent_app_type] => 1 [patent_app_number] => 9/624448 [patent_app_country] => US [patent_app_date] => 2000-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2513 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/259/06259652.pdf [firstpage_image] =>[orig_patent_app_number] => 624448 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/624448
Synchronous integrated memory Jul 23, 2000 Issued
Array ( [id] => 4344578 [patent_doc_number] => 06314017 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-06 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/621652 [patent_app_country] => US [patent_app_date] => 2000-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 44 [patent_no_of_words] => 13000 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/314/06314017.pdf [firstpage_image] =>[orig_patent_app_number] => 621652 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/621652
Semiconductor memory device Jul 20, 2000 Issued
Array ( [id] => 4359193 [patent_doc_number] => 06285618 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'Device and method for repairing a memory array by storing each bit in multiple memory cells in the array' [patent_app_type] => 1 [patent_app_number] => 9/618816 [patent_app_country] => US [patent_app_date] => 2000-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 8004 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 16 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/285/06285618.pdf [firstpage_image] =>[orig_patent_app_number] => 618816 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/618816
Device and method for repairing a memory array by storing each bit in multiple memory cells in the array Jul 17, 2000 Issued
Array ( [id] => 4298765 [patent_doc_number] => 06269047 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-31 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/618163 [patent_app_country] => US [patent_app_date] => 2000-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 23 [patent_no_of_words] => 12351 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/269/06269047.pdf [firstpage_image] =>[orig_patent_app_number] => 618163 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/618163
Semiconductor memory device Jul 16, 2000 Issued
Array ( [id] => 1600083 [patent_doc_number] => 06493263 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-10 [patent_title] => 'Semiconductor computing circuit and computing apparatus' [patent_app_type] => B1 [patent_app_number] => 09/615755 [patent_app_country] => US [patent_app_date] => 2000-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 9590 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/493/06493263.pdf [firstpage_image] =>[orig_patent_app_number] => 09615755 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/615755
Semiconductor computing circuit and computing apparatus Jul 12, 2000 Issued
Array ( [id] => 4346433 [patent_doc_number] => 06333891 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-25 [patent_title] => 'Circuit and method for controlling a wordline and/or stabilizing a memory cell' [patent_app_type] => 1 [patent_app_number] => 9/613949 [patent_app_country] => US [patent_app_date] => 2000-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1872 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/333/06333891.pdf [firstpage_image] =>[orig_patent_app_number] => 613949 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/613949
Circuit and method for controlling a wordline and/or stabilizing a memory cell Jul 10, 2000 Issued
Array ( [id] => 4373791 [patent_doc_number] => 06256222 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Magnetoresistance effect device, and magnetoresistaance effect type head, memory device, and amplifying device using the same' [patent_app_type] => 1 [patent_app_number] => 9/612805 [patent_app_country] => US [patent_app_date] => 2000-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 47 [patent_no_of_words] => 26903 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 291 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/256/06256222.pdf [firstpage_image] =>[orig_patent_app_number] => 612805 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/612805
Magnetoresistance effect device, and magnetoresistaance effect type head, memory device, and amplifying device using the same Jul 9, 2000 Issued
Array ( [id] => 4419951 [patent_doc_number] => 06229731 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Nonvolatile semiconductor memory device with security function and protect function' [patent_app_type] => 1 [patent_app_number] => 9/606146 [patent_app_country] => US [patent_app_date] => 2000-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 3784 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/229/06229731.pdf [firstpage_image] =>[orig_patent_app_number] => 606146 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/606146
Nonvolatile semiconductor memory device with security function and protect function Jun 28, 2000 Issued
Menu