Son Luu Mai

Array ( [id] => 4302406 [patent_doc_number] => 06212098 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'Voltage protection of write protect cams' [patent_app_type] => 1 [patent_app_number] => 9/602095 [patent_app_country] => US [patent_app_date] => 2000-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4715 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/212/06212098.pdf [firstpage_image] =>[orig_patent_app_number] => 602095 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4395226 [patent_doc_number] => 06278634 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'Reference memory cell initialization circuit and method' [patent_app_type] => 1 [patent_app_number] => 9/598211 [patent_app_country] => US [patent_app_date] => 2000-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6706 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/278/06278634.pdf [firstpage_image] =>[orig_patent_app_number] => 598211 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4298329 [patent_doc_number] => 06269016 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-31 [patent_title] => 'MRAM cam' [patent_app_type] => 1 [patent_app_number] => 9/597362 [patent_app_country] => US [patent_app_date] => 2000-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3876 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/269/06269016.pdf [firstpage_image] =>[orig_patent_app_number] => 597362 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4396932 [patent_doc_number] => 06262935 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'Shift redundancy scheme for wordlines in memory circuits' [patent_app_type] => 1 [patent_app_number] => 9/595149 [patent_app_country] => US [patent_app_date] => 2000-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3481 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/262/06262935.pdf [firstpage_image] =>[orig_patent_app_number] => 595149 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4359097 [patent_doc_number] => 06285611 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'Memory device having input and output sense amplifiers that occupy less circuit area' [patent_app_type] => 1 [patent_app_number] => 9/596331 [patent_app_country] => US [patent_app_date] => 2000-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3588 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/285/06285611.pdf [firstpage_image] =>[orig_patent_app_number] => 596331 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1437671 [patent_doc_number] => 06356481 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-12 [patent_title] => 'Row decoder for a nonvolatile memory with capability of selectively biasing word lines to positive or negative voltages' [patent_app_type] => B1 [patent_app_number] => 09/595054 [patent_app_country] => US [patent_app_date] => 2000-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 6243 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/356/06356481.pdf [firstpage_image] =>[orig_patent_app_number] => 09595054 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4326021 [patent_doc_number] => 06317350 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-13 [patent_title] => 'Hierarchical depth cascading of content addressable memory devices' [patent_app_type] => 1 [patent_app_number] => 9/595850 [patent_app_country] => US [patent_app_date] => 2000-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 21 [patent_no_of_words] => 12485 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/317/06317350.pdf [firstpage_image] =>[orig_patent_app_number] => 595850 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4372750 [patent_doc_number] => 06192005 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-20 [patent_title] => 'Clock control signal and output enable signal generator in semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/594354 [patent_app_country] => US [patent_app_date] => 2000-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 8100 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 405 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/192/06192005.pdf [firstpage_image] =>[orig_patent_app_number] => 594354 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4266176 [patent_doc_number] => 06208572 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-27 [patent_title] => 'Semiconductor memory device having resistive bitline contact testing' [patent_app_type] => 1 [patent_app_number] => 9/592055 [patent_app_country] => US [patent_app_date] => 2000-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2513 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/208/06208572.pdf [firstpage_image] =>[orig_patent_app_number] => 592055 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1493411 [patent_doc_number] => 06418067 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-09 [patent_title] => 'Semiconductor memory device suitable for merging with logic' [patent_app_type] => B1 [patent_app_number] => 09/592454 [patent_app_country] => US [patent_app_date] => 2000-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 47 [patent_figures_cnt] => 67 [patent_no_of_words] => 33294 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/418/06418067.pdf [firstpage_image] =>[orig_patent_app_number] => 09592454 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4418621 [patent_doc_number] => 06240008 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-29 [patent_title] => 'Read zero DRAM' [patent_app_type] => 1 [patent_app_number] => 9/590443 [patent_app_country] => US [patent_app_date] => 2000-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2975 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/240/06240008.pdf [firstpage_image] =>[orig_patent_app_number] => 590443 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4419942 [patent_doc_number] => 06266269 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'Three terminal non-volatile memory element' [patent_app_type] => 1 [patent_app_number] => 9/589337 [patent_app_country] => US [patent_app_date] => 2000-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4984 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/266/06266269.pdf [firstpage_image] =>[orig_patent_app_number] => 589337 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4302716 [patent_doc_number] => 06212117 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'Duplicate bitline self-time technique for reliable memory operation' [patent_app_type] => 1 [patent_app_number] => 9/588831 [patent_app_country] => US [patent_app_date] => 2000-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2756 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/212/06212117.pdf [firstpage_image] =>[orig_patent_app_number] => 588831 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4262957 [patent_doc_number] => 06222782 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'Control circuit for a bit line equalization signal in semiconductor memory' [patent_app_type] => 1 [patent_app_number] => 9/588550 [patent_app_country] => US [patent_app_date] => 2000-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2178 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/222/06222782.pdf [firstpage_image] =>[orig_patent_app_number] => 588550 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4416073 [patent_doc_number] => 06265920 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'Power/area efficient method for high-frequency pre-emphasis for intra-chip signaling' [patent_app_type] => 1 [patent_app_number] => 9/589027 [patent_app_country] => US [patent_app_date] => 2000-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 3363 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/265/06265920.pdf [firstpage_image] =>[orig_patent_app_number] => 589027 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4419018 [patent_doc_number] => 06301145 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-09 [patent_title] => 'Ferroelectric memory and method for accessing same' [patent_app_type] => 1 [patent_app_number] => 9/587253 [patent_app_country] => US [patent_app_date] => 2000-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 10704 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/301/06301145.pdf [firstpage_image] =>[orig_patent_app_number] => 587253 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4374098 [patent_doc_number] => 06256242 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Device and method for margin testing a semiconductor memory by applying a stressing voltage simultaneously to complementary and true digit lines' [patent_app_type] => 1 [patent_app_number] => 9/583478 [patent_app_country] => US [patent_app_date] => 2000-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2948 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/256/06256242.pdf [firstpage_image] =>[orig_patent_app_number] => 583478 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4358816 [patent_doc_number] => 06285592 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'Data storage device having superior data retention characteristic and method' [patent_app_type] => 1 [patent_app_number] => 9/580957 [patent_app_country] => US [patent_app_date] => 2000-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 8252 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/285/06285592.pdf [firstpage_image] =>[orig_patent_app_number] => 580957 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4309667 [patent_doc_number] => 06185131 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'Nonvolatile semiconductor storage device capable of electrically isolating dummy cell array region from memory cell array region' [patent_app_type] => 1 [patent_app_number] => 9/578852 [patent_app_country] => US [patent_app_date] => 2000-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6627 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/185/06185131.pdf [firstpage_image] =>[orig_patent_app_number] => 578852 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4291173 [patent_doc_number] => 06282136 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Semiconductor memory devices and sensors using the same' [patent_app_type] => 1 [patent_app_number] => 9/578854 [patent_app_country] => US [patent_app_date] => 2000-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6479 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/282/06282136.pdf [firstpage_image] =>[orig_patent_app_number] => 578854 [rel_patent_id] =>[rel_patent_doc_number] =>)