Son Luu Mai

Array ( [id] => 4302520 [patent_doc_number] => 06212105 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'Method for recording a binary word by means of electrically erasable and programmable type memory cells' [patent_app_type] => 1 [patent_app_number] => 9/523048 [patent_app_country] => US [patent_app_date] => 2000-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 8975 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/212/06212105.pdf [firstpage_image] =>[orig_patent_app_number] => 523048 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4262552 [patent_doc_number] => 06222755 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'Solid state holographic memory' [patent_app_type] => 1 [patent_app_number] => 9/520399 [patent_app_country] => US [patent_app_date] => 2000-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2934 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/222/06222755.pdf [firstpage_image] =>[orig_patent_app_number] => 520399 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4170157 [patent_doc_number] => 06157564 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-05 [patent_title] => 'Semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/519348 [patent_app_country] => US [patent_app_date] => 2000-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 32 [patent_no_of_words] => 9340 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/157/06157564.pdf [firstpage_image] =>[orig_patent_app_number] => 519348 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4363765 [patent_doc_number] => 06215714 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-10 [patent_title] => 'Semiconductor memory device capable of reducing power consumption in self-refresh operation' [patent_app_type] => 1 [patent_app_number] => 9/517279 [patent_app_country] => US [patent_app_date] => 2000-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5198 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/215/06215714.pdf [firstpage_image] =>[orig_patent_app_number] => 517279 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4339144 [patent_doc_number] => 06330183 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-11 [patent_title] => 'Dual conductor inductive sensor for a non-volatile random access ferromagnetic memory' [patent_app_type] => 1 [patent_app_number] => 9/516453 [patent_app_country] => US [patent_app_date] => 2000-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2300 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/330/06330183.pdf [firstpage_image] =>[orig_patent_app_number] => 516453 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4326079 [patent_doc_number] => 06317354 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-13 [patent_title] => 'Non-volatile random access ferromagnetic memory with single collector sensor' [patent_app_type] => 1 [patent_app_number] => 9/516046 [patent_app_country] => US [patent_app_date] => 2000-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3490 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/317/06317354.pdf [firstpage_image] =>[orig_patent_app_number] => 516046 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6223083 [patent_doc_number] => 20020003744 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-10 [patent_title] => 'Programmable low voltage decode circuits with ultra-thin tunnel oxides' [patent_app_type] => new [patent_app_number] => 09/515115 [patent_app_country] => US [patent_app_date] => 2000-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 11694 [patent_no_of_claims] => 69 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20020003744.pdf [firstpage_image] =>[orig_patent_app_number] => 09515115 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4393758 [patent_doc_number] => 06295228 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-25 [patent_title] => 'System for programming memory cells' [patent_app_type] => 1 [patent_app_number] => 9/514933 [patent_app_country] => US [patent_app_date] => 2000-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 7119 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/295/06295228.pdf [firstpage_image] =>[orig_patent_app_number] => 514933 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4302294 [patent_doc_number] => 06212091 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'Semiconductor memory device having a shielding line' [patent_app_type] => 1 [patent_app_number] => 9/514313 [patent_app_country] => US [patent_app_date] => 2000-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 4957 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/212/06212091.pdf [firstpage_image] =>[orig_patent_app_number] => 514313 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4418439 [patent_doc_number] => 06310798 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-30 [patent_title] => 'Semiconductor memory and method for manufacture thereof' [patent_app_type] => 1 [patent_app_number] => 9/513848 [patent_app_country] => US [patent_app_date] => 2000-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 8184 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/310/06310798.pdf [firstpage_image] =>[orig_patent_app_number] => 513848 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4252504 [patent_doc_number] => 06166981 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-26 [patent_title] => 'Method for addressing electrical fuses' [patent_app_type] => 1 [patent_app_number] => 9/512922 [patent_app_country] => US [patent_app_date] => 2000-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3643 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/166/06166981.pdf [firstpage_image] =>[orig_patent_app_number] => 512922 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4305359 [patent_doc_number] => 06236616 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'Semiconductor memory device having data input/output line shared by a plurality of banks' [patent_app_type] => 1 [patent_app_number] => 9/513713 [patent_app_country] => US [patent_app_date] => 2000-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 6096 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/236/06236616.pdf [firstpage_image] =>[orig_patent_app_number] => 513713 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4145409 [patent_doc_number] => 06147913 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-14 [patent_title] => 'Data transmission circuitry of a synchronous semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/513621 [patent_app_country] => US [patent_app_date] => 2000-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6737 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/147/06147913.pdf [firstpage_image] =>[orig_patent_app_number] => 513621 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4272673 [patent_doc_number] => 06205055 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-20 [patent_title] => 'Dynamic memory cell programming voltage' [patent_app_type] => 1 [patent_app_number] => 9/512854 [patent_app_country] => US [patent_app_date] => 2000-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1700 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/205/06205055.pdf [firstpage_image] =>[orig_patent_app_number] => 512854 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4265847 [patent_doc_number] => 06208549 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-27 [patent_title] => 'One-time programmable poly-fuse circuit for implementing non-volatile functions in a standard sub 0.35 micron CMOS' [patent_app_type] => 1 [patent_app_number] => 9/513235 [patent_app_country] => US [patent_app_date] => 2000-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4478 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/208/06208549.pdf [firstpage_image] =>[orig_patent_app_number] => 513235 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4426442 [patent_doc_number] => 06226223 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-01 [patent_title] => 'Low latency dynamic random access memory' [patent_app_type] => 1 [patent_app_number] => 9/511901 [patent_app_country] => US [patent_app_date] => 2000-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 20 [patent_no_of_words] => 9317 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/226/06226223.pdf [firstpage_image] =>[orig_patent_app_number] => 511901 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4305292 [patent_doc_number] => 06236612 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'Integrated semiconductor memory configuration with self-buffering of supply voltages' [patent_app_type] => 1 [patent_app_number] => 9/523146 [patent_app_country] => US [patent_app_date] => 2000-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1745 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/236/06236612.pdf [firstpage_image] =>[orig_patent_app_number] => 523146 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4327554 [patent_doc_number] => 06243308 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-05 [patent_title] => 'Method for testing dynamic random access memory under wafer-level-burn-in' [patent_app_type] => 1 [patent_app_number] => 9/511653 [patent_app_country] => US [patent_app_date] => 2000-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2263 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/243/06243308.pdf [firstpage_image] =>[orig_patent_app_number] => 511653 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4284788 [patent_doc_number] => 06246610 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-12 [patent_title] => 'Symmetrical program and erase scheme to improve erase time degradation in NAND devices' [patent_app_type] => 1 [patent_app_number] => 9/511652 [patent_app_country] => US [patent_app_date] => 2000-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 6959 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/246/06246610.pdf [firstpage_image] =>[orig_patent_app_number] => 511652 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4185763 [patent_doc_number] => 06141285 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-31 [patent_title] => 'Power down scheme for regulated sense amplifier power in dram' [patent_app_type] => 1 [patent_app_number] => 9/510946 [patent_app_country] => US [patent_app_date] => 2000-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1619 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/141/06141285.pdf [firstpage_image] =>[orig_patent_app_number] => 510946 [rel_patent_id] =>[rel_patent_doc_number] =>)