Son Luu Mai

Array ( [id] => 4140063 [patent_doc_number] => 06128217 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/431271 [patent_app_country] => US [patent_app_date] => 1999-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 14 [patent_no_of_words] => 5257 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/128/06128217.pdf [firstpage_image] =>[orig_patent_app_number] => 431271 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4145172 [patent_doc_number] => 06147896 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-14 [patent_title] => 'Nonvolatile ferroelectric memory using selective reference cell' [patent_app_type] => 1 [patent_app_number] => 9/429752 [patent_app_country] => US [patent_app_date] => 1999-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 2727 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/147/06147896.pdf [firstpage_image] =>[orig_patent_app_number] => 429752 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4197597 [patent_doc_number] => 06151243 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-21 [patent_title] => 'Ferroelectric memory device having folded bit line architecture' [patent_app_type] => 1 [patent_app_number] => 9/428546 [patent_app_country] => US [patent_app_date] => 1999-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 1380 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/151/06151243.pdf [firstpage_image] =>[orig_patent_app_number] => 428546 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4140090 [patent_doc_number] => 06128219 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'Nonvolatile memory test structure and nonvolatile memory reliability test method' [patent_app_type] => 1 [patent_app_number] => 9/428683 [patent_app_country] => US [patent_app_date] => 1999-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 22 [patent_no_of_words] => 6476 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/128/06128219.pdf [firstpage_image] =>[orig_patent_app_number] => 428683 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4185857 [patent_doc_number] => 06141291 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-31 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/425291 [patent_app_country] => US [patent_app_date] => 1999-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 23 [patent_no_of_words] => 12352 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/141/06141291.pdf [firstpage_image] =>[orig_patent_app_number] => 425291 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4425621 [patent_doc_number] => 06195303 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-27 [patent_title] => 'Clock-based transparent refresh mechanisms for DRAMS' [patent_app_type] => 1 [patent_app_number] => 9/427150 [patent_app_country] => US [patent_app_date] => 1999-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 6497 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/195/06195303.pdf [firstpage_image] =>[orig_patent_app_number] => 427150 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4368431 [patent_doc_number] => 06175523 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-16 [patent_title] => 'Precharging mechanism and method for NAND-based flash memory devices' [patent_app_type] => 1 [patent_app_number] => 9/433187 [patent_app_country] => US [patent_app_date] => 1999-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 23 [patent_no_of_words] => 4239 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/175/06175523.pdf [firstpage_image] =>[orig_patent_app_number] => 433187 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4425576 [patent_doc_number] => 06195289 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-27 [patent_title] => 'Device for reading analog nonvolatile memory cells, in particular flash cells' [patent_app_type] => 1 [patent_app_number] => 9/425446 [patent_app_country] => US [patent_app_date] => 1999-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2289 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/195/06195289.pdf [firstpage_image] =>[orig_patent_app_number] => 425446 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4308858 [patent_doc_number] => 06181591 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-30 [patent_title] => 'High speed CAM cell' [patent_app_type] => 1 [patent_app_number] => 9/417852 [patent_app_country] => US [patent_app_date] => 1999-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5484 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/181/06181591.pdf [firstpage_image] =>[orig_patent_app_number] => 417852 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4309086 [patent_doc_number] => 06181605 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-30 [patent_title] => 'Global erase/program verification apparatus and method' [patent_app_type] => 1 [patent_app_number] => 9/414750 [patent_app_country] => US [patent_app_date] => 1999-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2423 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/181/06181605.pdf [firstpage_image] =>[orig_patent_app_number] => 414750 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4374320 [patent_doc_number] => 06256258 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Semiconductor memory system, and access control method for semiconductor memory and semiconductor memory' [patent_app_type] => 1 [patent_app_number] => 9/411373 [patent_app_country] => US [patent_app_date] => 1999-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 8339 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/256/06256258.pdf [firstpage_image] =>[orig_patent_app_number] => 411373 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4368417 [patent_doc_number] => 06175522 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-16 [patent_title] => 'Read operation scheme for a high-density, low voltage, and superior reliability nand flash memory device' [patent_app_type] => 1 [patent_app_number] => 9/408846 [patent_app_country] => US [patent_app_date] => 1999-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3216 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/175/06175522.pdf [firstpage_image] =>[orig_patent_app_number] => 408846 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4290834 [patent_doc_number] => 06282113 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Four F-squared gapless dual layer bitline DRAM array architecture' [patent_app_type] => 1 [patent_app_number] => 9/408349 [patent_app_country] => US [patent_app_date] => 1999-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 2571 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/282/06282113.pdf [firstpage_image] =>[orig_patent_app_number] => 408349 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4316752 [patent_doc_number] => 06188598 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-13 [patent_title] => 'Reducing impact of coupling noise' [patent_app_type] => 1 [patent_app_number] => 9/406891 [patent_app_country] => US [patent_app_date] => 1999-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2842 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/188/06188598.pdf [firstpage_image] =>[orig_patent_app_number] => 406891 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4170435 [patent_doc_number] => 06104662 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-15 [patent_title] => 'Data masking systems and methods for integrated circuit memory devices including pulse-responsive equalizers and prechargers' [patent_app_type] => 1 [patent_app_number] => 9/405746 [patent_app_country] => US [patent_app_date] => 1999-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4644 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/104/06104662.pdf [firstpage_image] =>[orig_patent_app_number] => 405746 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4231691 [patent_doc_number] => 06088289 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'Circuit and method for controlling a wordline and/or stabilizing a memory cell' [patent_app_type] => 1 [patent_app_number] => 9/405950 [patent_app_country] => US [patent_app_date] => 1999-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1935 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/088/06088289.pdf [firstpage_image] =>[orig_patent_app_number] => 405950 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4252193 [patent_doc_number] => 06166960 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-26 [patent_title] => 'Method, system and apparatus for determining that a programming voltage level is sufficient for reliably programming an eeprom' [patent_app_type] => 1 [patent_app_number] => 9/405450 [patent_app_country] => US [patent_app_date] => 1999-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4166 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/166/06166960.pdf [firstpage_image] =>[orig_patent_app_number] => 405450 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4170088 [patent_doc_number] => 06108253 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-22 [patent_title] => 'Failure analysis system, fatal failure extraction method and recording medium' [patent_app_type] => 1 [patent_app_number] => 9/401848 [patent_app_country] => US [patent_app_date] => 1999-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 54 [patent_no_of_words] => 17254 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 406 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/108/06108253.pdf [firstpage_image] =>[orig_patent_app_number] => 401848 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4170227 [patent_doc_number] => 06104648 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-15 [patent_title] => 'Semiconductor memory device having a large band width and allowing efficient execution of redundant repair' [patent_app_type] => 1 [patent_app_number] => 9/400848 [patent_app_country] => US [patent_app_date] => 1999-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 27 [patent_no_of_words] => 16831 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 285 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/104/06104648.pdf [firstpage_image] =>[orig_patent_app_number] => 400848 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4147969 [patent_doc_number] => 06122208 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-19 [patent_title] => 'Circuit and method for column redundancy for high bandwidth memories' [patent_app_type] => 1 [patent_app_number] => 9/398252 [patent_app_country] => US [patent_app_date] => 1999-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2866 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/122/06122208.pdf [firstpage_image] =>[orig_patent_app_number] => 398252 [rel_patent_id] =>[rel_patent_doc_number] =>)