Search

Son Luu Mai

Examiner (ID: 18155)

Most Active Art Unit
2827
Art Unit(s)
2511, 2827, 2818
Total Applications
3063
Issued Applications
2917
Pending Applications
45
Abandoned Applications
107

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4261943 [patent_doc_number] => 06137741 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Sense amplifier with cascode output' [patent_app_type] => 1 [patent_app_number] => 9/397754 [patent_app_country] => US [patent_app_date] => 1999-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3424 [patent_no_of_claims] => 78 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/137/06137741.pdf [firstpage_image] =>[orig_patent_app_number] => 397754 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/397754
Sense amplifier with cascode output Sep 15, 1999 Issued
Array ( [id] => 4117155 [patent_doc_number] => 06101139 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-08 [patent_title] => 'Device and method for margin testing a semiconductor memory by applying a stressing voltage simultaneously to complementary and true digit lines' [patent_app_type] => 1 [patent_app_number] => 9/392154 [patent_app_country] => US [patent_app_date] => 1999-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2949 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/101/06101139.pdf [firstpage_image] =>[orig_patent_app_number] => 392154 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/392154
Device and method for margin testing a semiconductor memory by applying a stressing voltage simultaneously to complementary and true digit lines Sep 7, 1999 Issued
Array ( [id] => 4131342 [patent_doc_number] => 06072734 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-06 [patent_title] => 'Read only memory having bias circuits' [patent_app_type] => 1 [patent_app_number] => 9/389648 [patent_app_country] => US [patent_app_date] => 1999-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 1873 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/072/06072734.pdf [firstpage_image] =>[orig_patent_app_number] => 389648 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/389648
Read only memory having bias circuits Sep 1, 1999 Issued
Array ( [id] => 4250558 [patent_doc_number] => 06144593 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-07 [patent_title] => 'Circuit and method for a multiplexed redundancy scheme in a memory device' [patent_app_type] => 1 [patent_app_number] => 9/387650 [patent_app_country] => US [patent_app_date] => 1999-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4322 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/144/06144593.pdf [firstpage_image] =>[orig_patent_app_number] => 387650 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/387650
Circuit and method for a multiplexed redundancy scheme in a memory device Aug 31, 1999 Issued
Array ( [id] => 4093389 [patent_doc_number] => 06055184 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-25 [patent_title] => 'Semiconductor memory device having programmable parallel erase operation' [patent_app_type] => 1 [patent_app_number] => 9/388046 [patent_app_country] => US [patent_app_date] => 1999-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4954 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/055/06055184.pdf [firstpage_image] =>[orig_patent_app_number] => 388046 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/388046
Semiconductor memory device having programmable parallel erase operation Aug 31, 1999 Issued
Array ( [id] => 4416974 [patent_doc_number] => 06233190 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-15 [patent_title] => 'Method of storing a temperature threshold in an integrated circuit, method of modifying operation of dynamic random access memory in response to temperature, programmable temperature sensing circuit and memory integrated circuit' [patent_app_type] => 1 [patent_app_number] => 9/386075 [patent_app_country] => US [patent_app_date] => 1999-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 6234 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/233/06233190.pdf [firstpage_image] =>[orig_patent_app_number] => 386075 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/386075
Method of storing a temperature threshold in an integrated circuit, method of modifying operation of dynamic random access memory in response to temperature, programmable temperature sensing circuit and memory integrated circuit Aug 29, 1999 Issued
Array ( [id] => 4169787 [patent_doc_number] => 06108233 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-22 [patent_title] => 'Ultra low voltage static RAM memory cell' [patent_app_type] => 1 [patent_app_number] => 9/384346 [patent_app_country] => US [patent_app_date] => 1999-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4488 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/108/06108233.pdf [firstpage_image] =>[orig_patent_app_number] => 384346 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/384346
Ultra low voltage static RAM memory cell Aug 26, 1999 Issued
Array ( [id] => 4127094 [patent_doc_number] => 06046957 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-04 [patent_title] => 'Semiconductor memory device with flexible configuration' [patent_app_type] => 1 [patent_app_number] => 9/384045 [patent_app_country] => US [patent_app_date] => 1999-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 4825 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 437 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/046/06046957.pdf [firstpage_image] =>[orig_patent_app_number] => 384045 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/384045
Semiconductor memory device with flexible configuration Aug 25, 1999 Issued
09/382570 APPARATUS FOR ON-BOARD PROGRAMMING OF SERIAL EEPROMS Aug 24, 1999 Abandoned
Array ( [id] => 4252208 [patent_doc_number] => 06166961 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-26 [patent_title] => 'Approach to provide high external voltage for flash memory erase' [patent_app_type] => 1 [patent_app_number] => 9/377545 [patent_app_country] => US [patent_app_date] => 1999-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3062 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/166/06166961.pdf [firstpage_image] =>[orig_patent_app_number] => 377545 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/377545
Approach to provide high external voltage for flash memory erase Aug 18, 1999 Issued
Array ( [id] => 4170167 [patent_doc_number] => 06108258 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-22 [patent_title] => 'Sense amplifier for high-speed integrated circuit memory device' [patent_app_type] => 1 [patent_app_number] => 9/378241 [patent_app_country] => US [patent_app_date] => 1999-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 2733 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/108/06108258.pdf [firstpage_image] =>[orig_patent_app_number] => 378241 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/378241
Sense amplifier for high-speed integrated circuit memory device Aug 18, 1999 Issued
Array ( [id] => 4420088 [patent_doc_number] => 06266282 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'Write method of synchronous flash memory device sharing a system bus with a synchronous random access memory device' [patent_app_type] => 1 [patent_app_number] => 9/373444 [patent_app_country] => US [patent_app_date] => 1999-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2680 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/266/06266282.pdf [firstpage_image] =>[orig_patent_app_number] => 373444 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/373444
Write method of synchronous flash memory device sharing a system bus with a synchronous random access memory device Aug 11, 1999 Issued
Array ( [id] => 4120484 [patent_doc_number] => 06058048 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-02 [patent_title] => 'Flash memory device used as a boot-up memory in a computer system' [patent_app_type] => 1 [patent_app_number] => 9/372345 [patent_app_country] => US [patent_app_date] => 1999-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3003 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/058/06058048.pdf [firstpage_image] =>[orig_patent_app_number] => 372345 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/372345
Flash memory device used as a boot-up memory in a computer system Aug 10, 1999 Issued
Array ( [id] => 4309104 [patent_doc_number] => 06198661 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-06 [patent_title] => 'Sensing circuit for semiconductor device and sensing method using the same' [patent_app_type] => 1 [patent_app_number] => 9/371042 [patent_app_country] => US [patent_app_date] => 1999-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 4453 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/198/06198661.pdf [firstpage_image] =>[orig_patent_app_number] => 371042 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/371042
Sensing circuit for semiconductor device and sensing method using the same Aug 9, 1999 Issued
Array ( [id] => 4140283 [patent_doc_number] => 06128233 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'Data transmission circuitry of a synchronous semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/370842 [patent_app_country] => US [patent_app_date] => 1999-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4716 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/128/06128233.pdf [firstpage_image] =>[orig_patent_app_number] => 370842 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/370842
Data transmission circuitry of a synchronous semiconductor memory device Aug 8, 1999 Issued
Array ( [id] => 4102733 [patent_doc_number] => 06134153 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-17 [patent_title] => 'Bi-directional data bus scheme with optimized read and write characters' [patent_app_type] => 1 [patent_app_number] => 9/364181 [patent_app_country] => US [patent_app_date] => 1999-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7218 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/134/06134153.pdf [firstpage_image] =>[orig_patent_app_number] => 364181 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/364181
Bi-directional data bus scheme with optimized read and write characters Jul 28, 1999 Issued
Array ( [id] => 4169702 [patent_doc_number] => 06108227 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-22 [patent_title] => 'Content addressable memory having binary and ternary modes of operation' [patent_app_type] => 1 [patent_app_number] => 9/359848 [patent_app_country] => US [patent_app_date] => 1999-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 5954 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/108/06108227.pdf [firstpage_image] =>[orig_patent_app_number] => 359848 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/359848
Content addressable memory having binary and ternary modes of operation Jul 22, 1999 Issued
Array ( [id] => 4216956 [patent_doc_number] => 06078533 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-20 [patent_title] => 'Adjustable delay circuit for setting the speed grade of a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/358739 [patent_app_country] => US [patent_app_date] => 1999-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2873 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/078/06078533.pdf [firstpage_image] =>[orig_patent_app_number] => 358739 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/358739
Adjustable delay circuit for setting the speed grade of a semiconductor device Jul 20, 1999 Issued
Array ( [id] => 4250646 [patent_doc_number] => 06081462 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-27 [patent_title] => 'Adjustable delay circuit for setting the speed grade of a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/362628 [patent_app_country] => US [patent_app_date] => 1999-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2873 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/081/06081462.pdf [firstpage_image] =>[orig_patent_app_number] => 362628 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/362628
Adjustable delay circuit for setting the speed grade of a semiconductor device Jul 20, 1999 Issued
Array ( [id] => 4309203 [patent_doc_number] => 06198668 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-06 [patent_title] => 'Memory cell array for performing a comparison' [patent_app_type] => 1 [patent_app_number] => 9/356485 [patent_app_country] => US [patent_app_date] => 1999-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4379 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/198/06198668.pdf [firstpage_image] =>[orig_patent_app_number] => 356485 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/356485
Memory cell array for performing a comparison Jul 18, 1999 Issued
Menu