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Son Luu Mai

Examiner (ID: 18155)

Most Active Art Unit
2827
Art Unit(s)
2511, 2827, 2818
Total Applications
3063
Issued Applications
2917
Pending Applications
45
Abandoned Applications
107

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4185603 [patent_doc_number] => 06141274 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-31 [patent_title] => 'Semiconductor integrated circuit having a pre-charged operation and a data latch function' [patent_app_type] => 1 [patent_app_number] => 9/340145 [patent_app_country] => US [patent_app_date] => 1999-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8524 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/141/06141274.pdf [firstpage_image] =>[orig_patent_app_number] => 340145 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/340145
Semiconductor integrated circuit having a pre-charged operation and a data latch function Jun 27, 1999 Issued
Array ( [id] => 4117118 [patent_doc_number] => 06101137 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-08 [patent_title] => 'Semiconductor memory device having delay locked loop (DLL)' [patent_app_type] => 1 [patent_app_number] => 9/338545 [patent_app_country] => US [patent_app_date] => 1999-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 4580 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/101/06101137.pdf [firstpage_image] =>[orig_patent_app_number] => 338545 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/338545
Semiconductor memory device having delay locked loop (DLL) Jun 22, 1999 Issued
Array ( [id] => 4251841 [patent_doc_number] => 06091646 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-18 [patent_title] => 'Method and apparatus for coupling data from a memory device using a single ended read data path' [patent_app_type] => 1 [patent_app_number] => 9/336391 [patent_app_country] => US [patent_app_date] => 1999-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3544 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/091/06091646.pdf [firstpage_image] =>[orig_patent_app_number] => 336391 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/336391
Method and apparatus for coupling data from a memory device using a single ended read data path Jun 17, 1999 Issued
Array ( [id] => 4152759 [patent_doc_number] => 06061266 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-09 [patent_title] => 'Ferroelectric random access memory device including active read/write circuit' [patent_app_type] => 1 [patent_app_number] => 9/335241 [patent_app_country] => US [patent_app_date] => 1999-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 3883 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/061/06061266.pdf [firstpage_image] =>[orig_patent_app_number] => 335241 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/335241
Ferroelectric random access memory device including active read/write circuit Jun 16, 1999 Issued
Array ( [id] => 4093243 [patent_doc_number] => 06055174 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-25 [patent_title] => 'Solid state holographic memory' [patent_app_type] => 1 [patent_app_number] => 9/327146 [patent_app_country] => US [patent_app_date] => 1999-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2935 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/055/06055174.pdf [firstpage_image] =>[orig_patent_app_number] => 327146 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/327146
Solid state holographic memory Jun 6, 1999 Issued
Array ( [id] => 4197295 [patent_doc_number] => 06094387 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-25 [patent_title] => 'Roll call tester' [patent_app_type] => 1 [patent_app_number] => 9/325041 [patent_app_country] => US [patent_app_date] => 1999-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5605 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/094/06094387.pdf [firstpage_image] =>[orig_patent_app_number] => 325041 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/325041
Roll call tester Jun 2, 1999 Issued
Array ( [id] => 4110866 [patent_doc_number] => 06067265 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-23 [patent_title] => 'Reference potential generator and a semiconductor memory device having the same' [patent_app_type] => 1 [patent_app_number] => 9/323894 [patent_app_country] => US [patent_app_date] => 1999-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 30 [patent_no_of_words] => 11566 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/067/06067265.pdf [firstpage_image] =>[orig_patent_app_number] => 323894 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/323894
Reference potential generator and a semiconductor memory device having the same Jun 1, 1999 Issued
Array ( [id] => 4424313 [patent_doc_number] => 06177807 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-23 [patent_title] => 'High frequency valid data strobe' [patent_app_type] => 1 [patent_app_number] => 9/322465 [patent_app_country] => US [patent_app_date] => 1999-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 3998 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/177/06177807.pdf [firstpage_image] =>[orig_patent_app_number] => 322465 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/322465
High frequency valid data strobe May 27, 1999 Issued
Array ( [id] => 4229810 [patent_doc_number] => 06111791 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-29 [patent_title] => 'Circuit device and corresponding method for programming a nonvolatile memory cell having a single voltage supply' [patent_app_type] => 1 [patent_app_number] => 9/322644 [patent_app_country] => US [patent_app_date] => 1999-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4396 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/111/06111791.pdf [firstpage_image] =>[orig_patent_app_number] => 322644 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/322644
Circuit device and corresponding method for programming a nonvolatile memory cell having a single voltage supply May 27, 1999 Issued
Array ( [id] => 4299559 [patent_doc_number] => 06236230 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'Method, architecture and circuit for product term allocation' [patent_app_type] => 1 [patent_app_number] => 9/322946 [patent_app_country] => US [patent_app_date] => 1999-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 6093 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/236/06236230.pdf [firstpage_image] =>[orig_patent_app_number] => 322946 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/322946
Method, architecture and circuit for product term allocation May 27, 1999 Issued
Array ( [id] => 4309268 [patent_doc_number] => 06198673 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-06 [patent_title] => 'Semiconductor integrated circuit having a unit cell including NMOS and PMOS transistors' [patent_app_type] => 1 [patent_app_number] => 9/321532 [patent_app_country] => US [patent_app_date] => 1999-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 28 [patent_no_of_words] => 6203 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/198/06198673.pdf [firstpage_image] =>[orig_patent_app_number] => 321532 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/321532
Semiconductor integrated circuit having a unit cell including NMOS and PMOS transistors May 27, 1999 Issued
Array ( [id] => 4424320 [patent_doc_number] => 06177809 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-23 [patent_title] => 'Redundant input/output driver circuit' [patent_app_type] => 1 [patent_app_number] => 9/322470 [patent_app_country] => US [patent_app_date] => 1999-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3027 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/177/06177809.pdf [firstpage_image] =>[orig_patent_app_number] => 322470 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/322470
Redundant input/output driver circuit May 27, 1999 Issued
Array ( [id] => 4163808 [patent_doc_number] => 06107832 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-22 [patent_title] => 'Input/output circuit' [patent_app_type] => 1 [patent_app_number] => 9/322167 [patent_app_country] => US [patent_app_date] => 1999-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 15134 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/107/06107832.pdf [firstpage_image] =>[orig_patent_app_number] => 322167 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/322167
Input/output circuit May 27, 1999 Issued
Array ( [id] => 4322012 [patent_doc_number] => 06242941 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-05 [patent_title] => 'Reducing I/O noise when leaving programming mode' [patent_app_type] => 1 [patent_app_number] => 9/320858 [patent_app_country] => US [patent_app_date] => 1999-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5726 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/242/06242941.pdf [firstpage_image] =>[orig_patent_app_number] => 320858 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/320858
Reducing I/O noise when leaving programming mode May 25, 1999 Issued
Array ( [id] => 4091208 [patent_doc_number] => 06163166 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-19 [patent_title] => 'Programmable logic device with selectable schmitt-triggered and threshold-triggered buffers' [patent_app_type] => 1 [patent_app_number] => 9/321257 [patent_app_country] => US [patent_app_date] => 1999-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1504 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/163/06163166.pdf [firstpage_image] =>[orig_patent_app_number] => 321257 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/321257
Programmable logic device with selectable schmitt-triggered and threshold-triggered buffers May 25, 1999 Issued
Array ( [id] => 4362968 [patent_doc_number] => 06218859 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Programmable logic device having quadrant layout' [patent_app_type] => 1 [patent_app_number] => 9/320007 [patent_app_country] => US [patent_app_date] => 1999-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5384 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/218/06218859.pdf [firstpage_image] =>[orig_patent_app_number] => 320007 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/320007
Programmable logic device having quadrant layout May 25, 1999 Issued
Array ( [id] => 4091637 [patent_doc_number] => 06163195 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-19 [patent_title] => 'Temperature compensated delay chain' [patent_app_type] => 1 [patent_app_number] => 9/318376 [patent_app_country] => US [patent_app_date] => 1999-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4475 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/163/06163195.pdf [firstpage_image] =>[orig_patent_app_number] => 318376 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/318376
Temperature compensated delay chain May 25, 1999 Issued
Array ( [id] => 4247134 [patent_doc_number] => 06118693 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-12 [patent_title] => 'Electrically erasable non-volatile memory cell with integrated SRAM cell to reduce testing time' [patent_app_type] => 1 [patent_app_number] => 9/320389 [patent_app_country] => US [patent_app_date] => 1999-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2975 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/118/06118693.pdf [firstpage_image] =>[orig_patent_app_number] => 320389 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/320389
Electrically erasable non-volatile memory cell with integrated SRAM cell to reduce testing time May 25, 1999 Issued
Array ( [id] => 4363547 [patent_doc_number] => 06215699 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-10 [patent_title] => 'Nonvolatile semiconductor storage device having main block and redundancy block formed on different wells' [patent_app_type] => 1 [patent_app_number] => 9/317821 [patent_app_country] => US [patent_app_date] => 1999-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 7335 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/215/06215699.pdf [firstpage_image] =>[orig_patent_app_number] => 317821 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/317821
Nonvolatile semiconductor storage device having main block and redundancy block formed on different wells May 24, 1999 Issued
Array ( [id] => 4117224 [patent_doc_number] => 06101144 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-08 [patent_title] => 'Integrated circuit memory devices having automatically induced standby modes and methods of operating same' [patent_app_type] => 1 [patent_app_number] => 9/318187 [patent_app_country] => US [patent_app_date] => 1999-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1968 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/101/06101144.pdf [firstpage_image] =>[orig_patent_app_number] => 318187 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/318187
Integrated circuit memory devices having automatically induced standby modes and methods of operating same May 24, 1999 Issued
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