
Son Luu Mai
Examiner (ID: 18155)
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2511, 2827, 2818 |
| Total Applications | 3063 |
| Issued Applications | 2917 |
| Pending Applications | 45 |
| Abandoned Applications | 107 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4296312
[patent_doc_number] => 06211697
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[patent_issue_date] => 2001-04-03
[patent_title] => 'Integrated circuit that includes a field-programmable gate array and a hard gate array having the same underlying structure'
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[patent_app_number] => 9/318198
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/318198 | Integrated circuit that includes a field-programmable gate array and a hard gate array having the same underlying structure | May 24, 1999 | Issued |
Array
(
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[patent_issue_date] => 2001-03-27
[patent_title] => 'EPROM and flash memory cells with source-side injection and a gate dielectric that traps hot electrons during programming'
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Array
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[patent_issue_date] => 2000-12-26
[patent_title] => 'Multi-bank testing apparatus for a synchronous DRAM'
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[patent_app_number] => 9/316389
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Array
(
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[patent_issue_date] => 2000-09-12
[patent_title] => 'Method and apparatus capable of trimming a nonvolatile semiconductor storage device without any superfluous pads or terminals'
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[patent_app_number] => 9/313989
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Array
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[patent_issue_date] => 2000-05-23
[patent_title] => 'Method to avoid program disturb and allow shrinking the cell size in split gate flash memory'
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Array
(
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[patent_doc_number] => 06055179
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[patent_issue_date] => 2000-04-25
[patent_title] => 'Memory device utilizing giant magnetoresistance effect'
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Array
(
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[patent_issue_date] => 2001-11-13
[patent_title] => 'Vertical bipolar read access for low voltage memory cell'
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[patent_app_number] => 9/328074
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/328074 | Vertical bipolar read access for low voltage memory cell | May 7, 1999 | Issued |
Array
(
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[patent_doc_number] => 06111779
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[patent_issue_date] => 2000-08-29
[patent_title] => 'Cell structure for low electric power static RAM'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/304643 | Cell structure for low electric power static RAM | May 3, 1999 | Issued |
Array
(
[id] => 4273091
[patent_doc_number] => 06205082
[patent_country] => US
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[patent_issue_date] => 2001-03-20
[patent_title] => 'LSI device with memory and logics mounted thereon'
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Array
(
[id] => 4110050
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[patent_issue_date] => 2000-08-01
[patent_title] => 'Memory cell array architecture for random access memory device'
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Array
(
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[patent_title] => 'Semiconductor integrated circuit device and method of activating the same'
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Array
(
[id] => 4126824
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Array
(
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Array
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Array
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Array
(
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Array
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Array
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Array
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