Son Luu Mai

Array ( [id] => 4126653 [patent_doc_number] => 06046928 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-04 [patent_title] => 'Non-volatile semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/272942 [patent_app_country] => US [patent_app_date] => 1999-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4711 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/046/06046928.pdf [firstpage_image] =>[orig_patent_app_number] => 272942 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4170465 [patent_doc_number] => 06104664 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-15 [patent_title] => 'Memory address generator circuit and semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/268943 [patent_app_country] => US [patent_app_date] => 1999-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7455 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/104/06104664.pdf [firstpage_image] =>[orig_patent_app_number] => 268943 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4229665 [patent_doc_number] => 06111782 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-29 [patent_title] => 'Magnetoresistance effect device, and magnetoresistance effect type head, memory device, and amplifying device using the same' [patent_app_type] => 1 [patent_app_number] => 9/270647 [patent_app_country] => US [patent_app_date] => 1999-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 47 [patent_no_of_words] => 26846 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/111/06111782.pdf [firstpage_image] =>[orig_patent_app_number] => 270647 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4372212 [patent_doc_number] => 06191971 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-20 [patent_title] => 'Ferroelectric memory device' [patent_app_type] => 1 [patent_app_number] => 9/268687 [patent_app_country] => US [patent_app_date] => 1999-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 23 [patent_no_of_words] => 9865 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/191/06191971.pdf [firstpage_image] =>[orig_patent_app_number] => 268687 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4202185 [patent_doc_number] => 06154393 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-28 [patent_title] => 'Semiconductor memory device of double-data rate mode' [patent_app_type] => 1 [patent_app_number] => 9/268688 [patent_app_country] => US [patent_app_date] => 1999-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 6842 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/154/06154393.pdf [firstpage_image] =>[orig_patent_app_number] => 268688 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4250328 [patent_doc_number] => 06081442 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-27 [patent_title] => 'Contents addressable memory circuit for retrieval operation in units of data blocks' [patent_app_type] => 1 [patent_app_number] => 9/265889 [patent_app_country] => US [patent_app_date] => 1999-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4501 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/081/06081442.pdf [firstpage_image] =>[orig_patent_app_number] => 265889 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4131443 [patent_doc_number] => 06072741 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-06 [patent_title] => 'First-in, first-out integrated circuit memory device incorporating a retransmit function' [patent_app_type] => 1 [patent_app_number] => 9/266472 [patent_app_country] => US [patent_app_date] => 1999-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 11336 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/072/06072741.pdf [firstpage_image] =>[orig_patent_app_number] => 266472 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1554912 [patent_doc_number] => 06348805 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-19 [patent_title] => 'Method and apparatus for assigning pins for electrical testing of printed circuit boards' [patent_app_type] => B1 [patent_app_number] => 09/265666 [patent_app_country] => US [patent_app_date] => 1999-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 5543 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/348/06348805.pdf [firstpage_image] =>[orig_patent_app_number] => 09265666 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4426402 [patent_doc_number] => 06226206 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-01 [patent_title] => 'Semiconductor memory device including boost circuit' [patent_app_type] => 1 [patent_app_number] => 9/265042 [patent_app_country] => US [patent_app_date] => 1999-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4085 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/226/06226206.pdf [firstpage_image] =>[orig_patent_app_number] => 265042 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4145184 [patent_doc_number] => 06147898 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-14 [patent_title] => 'Semiconductor static random access memory device with low power consumption in a write operation' [patent_app_type] => 1 [patent_app_number] => 9/263089 [patent_app_country] => US [patent_app_date] => 1999-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4811 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/147/06147898.pdf [firstpage_image] =>[orig_patent_app_number] => 263089 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4155418 [patent_doc_number] => 06031780 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-29 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/262342 [patent_app_country] => US [patent_app_date] => 1999-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5614 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/031/06031780.pdf [firstpage_image] =>[orig_patent_app_number] => 262342 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4230636 [patent_doc_number] => 06041003 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-21 [patent_title] => 'Circuit and method for memory device with defect current isolation' [patent_app_type] => 1 [patent_app_number] => 9/261607 [patent_app_country] => US [patent_app_date] => 1999-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5604 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/041/06041003.pdf [firstpage_image] =>[orig_patent_app_number] => 261607 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4316844 [patent_doc_number] => 06188605 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-13 [patent_title] => 'Non-volatile semiconductor memory using split bit lines' [patent_app_type] => 1 [patent_app_number] => 9/257242 [patent_app_country] => US [patent_app_date] => 1999-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5163 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/188/06188605.pdf [firstpage_image] =>[orig_patent_app_number] => 257242 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4191777 [patent_doc_number] => 06038162 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-14 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/256941 [patent_app_country] => US [patent_app_date] => 1999-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 6307 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/038/06038162.pdf [firstpage_image] =>[orig_patent_app_number] => 256941 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4246195 [patent_doc_number] => 06075741 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-13 [patent_title] => 'Multiple staged power up of integrated circuit' [patent_app_type] => 1 [patent_app_number] => 9/253626 [patent_app_country] => US [patent_app_date] => 1999-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4729 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 15 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/075/06075741.pdf [firstpage_image] =>[orig_patent_app_number] => 253626 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4217032 [patent_doc_number] => 06078539 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-20 [patent_title] => 'Method and device for initiating a memory array during power up' [patent_app_type] => 1 [patent_app_number] => 9/244445 [patent_app_country] => US [patent_app_date] => 1999-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 5060 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/078/06078539.pdf [firstpage_image] =>[orig_patent_app_number] => 244445 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4185488 [patent_doc_number] => 06141267 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-31 [patent_title] => 'Defect management engine for semiconductor memories and memory systems' [patent_app_type] => 1 [patent_app_number] => 9/243645 [patent_app_country] => US [patent_app_date] => 1999-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 7831 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/141/06141267.pdf [firstpage_image] =>[orig_patent_app_number] => 243645 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4155058 [patent_doc_number] => 06031759 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-29 [patent_title] => 'Nonvolatile semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/243141 [patent_app_country] => US [patent_app_date] => 1999-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 5967 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/031/06031759.pdf [firstpage_image] =>[orig_patent_app_number] => 243141 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4233940 [patent_doc_number] => 06011719 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-04 [patent_title] => 'Digital signal processor having an on-chip pipelined EEPROM data memory and a on-chip pipelined EEPROM program memory' [patent_app_type] => 1 [patent_app_number] => 9/241150 [patent_app_country] => US [patent_app_date] => 1999-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6354 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/011/06011719.pdf [firstpage_image] =>[orig_patent_app_number] => 241150 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4247629 [patent_doc_number] => 06118728 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-12 [patent_title] => 'Circuit and method for memory device with defect current isolation' [patent_app_type] => 1 [patent_app_number] => 9/237362 [patent_app_country] => US [patent_app_date] => 1999-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5604 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/118/06118728.pdf [firstpage_image] =>[orig_patent_app_number] => 237362 [rel_patent_id] =>[rel_patent_doc_number] =>)