Search

Son Luu Mai

Examiner (ID: 18155)

Most Active Art Unit
2827
Art Unit(s)
2511, 2827, 2818
Total Applications
3063
Issued Applications
2917
Pending Applications
45
Abandoned Applications
107

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3993817 [patent_doc_number] => 05949706 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-07 [patent_title] => 'Static random access memory cell having a thin film transistor (TFT) pass gate connection to a bit line' [patent_app_type] => 1 [patent_app_number] => 9/236914 [patent_app_country] => US [patent_app_date] => 1999-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 14 [patent_no_of_words] => 5460 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/949/05949706.pdf [firstpage_image] =>[orig_patent_app_number] => 236914 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/236914
Static random access memory cell having a thin film transistor (TFT) pass gate connection to a bit line Jan 25, 1999 Issued
Array ( [id] => 3925320 [patent_doc_number] => 06002627 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-14 [patent_title] => 'Integrated circuit with temperature detector' [patent_app_type] => 1 [patent_app_number] => 9/237484 [patent_app_country] => US [patent_app_date] => 1999-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3221 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/002/06002627.pdf [firstpage_image] =>[orig_patent_app_number] => 237484 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/237484
Integrated circuit with temperature detector Jan 25, 1999 Issued
Array ( [id] => 4251779 [patent_doc_number] => 06091642 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-18 [patent_title] => 'Method for controlled erasing memory devices, in particular analog and multi-level flash-EEPROM devices' [patent_app_type] => 1 [patent_app_number] => 9/234942 [patent_app_country] => US [patent_app_date] => 1999-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2837 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/091/06091642.pdf [firstpage_image] =>[orig_patent_app_number] => 234942 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/234942
Method for controlled erasing memory devices, in particular analog and multi-level flash-EEPROM devices Jan 20, 1999 Issued
Array ( [id] => 4170508 [patent_doc_number] => 06157588 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-05 [patent_title] => 'Semiconductor memory device having hierarchical word line structure' [patent_app_type] => 1 [patent_app_number] => 9/229343 [patent_app_country] => US [patent_app_date] => 1999-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 7516 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/157/06157588.pdf [firstpage_image] =>[orig_patent_app_number] => 229343 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/229343
Semiconductor memory device having hierarchical word line structure Jan 12, 1999 Issued
Array ( [id] => 4144153 [patent_doc_number] => 06034885 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-07 [patent_title] => 'Multilevel memory cell sense amplifier system and sensing methods' [patent_app_type] => 1 [patent_app_number] => 9/229387 [patent_app_country] => US [patent_app_date] => 1999-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6297 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/034/06034885.pdf [firstpage_image] =>[orig_patent_app_number] => 229387 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/229387
Multilevel memory cell sense amplifier system and sensing methods Jan 10, 1999 Issued
Array ( [id] => 4171735 [patent_doc_number] => 06115310 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-05 [patent_title] => 'Wordline activation delay monitor using sample wordline located in data-storing array' [patent_app_type] => 1 [patent_app_number] => 9/225343 [patent_app_country] => US [patent_app_date] => 1999-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 5401 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/115/06115310.pdf [firstpage_image] =>[orig_patent_app_number] => 225343 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/225343
Wordline activation delay monitor using sample wordline located in data-storing array Jan 4, 1999 Issued
Array ( [id] => 4093489 [patent_doc_number] => 06055191 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-25 [patent_title] => 'Method and apparatus for leakage blocking' [patent_app_type] => 1 [patent_app_number] => 9/225133 [patent_app_country] => US [patent_app_date] => 1999-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 5201 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/055/06055191.pdf [firstpage_image] =>[orig_patent_app_number] => 225133 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/225133
Method and apparatus for leakage blocking Jan 3, 1999 Issued
Array ( [id] => 4197119 [patent_doc_number] => 06094375 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-25 [patent_title] => 'Integrated circuit memory devices having multiple data rate mode capability and methods of operating same' [patent_app_type] => 1 [patent_app_number] => 9/223541 [patent_app_country] => US [patent_app_date] => 1998-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 5682 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/094/06094375.pdf [firstpage_image] =>[orig_patent_app_number] => 223541 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/223541
Integrated circuit memory devices having multiple data rate mode capability and methods of operating same Dec 29, 1998 Issued
Array ( [id] => 4197187 [patent_doc_number] => 06094380 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-25 [patent_title] => 'Memory device with a data output buffer and the control method thereof' [patent_app_type] => 1 [patent_app_number] => 9/221344 [patent_app_country] => US [patent_app_date] => 1998-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 3733 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/094/06094380.pdf [firstpage_image] =>[orig_patent_app_number] => 221344 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/221344
Memory device with a data output buffer and the control method thereof Dec 27, 1998 Issued
Array ( [id] => 4290985 [patent_doc_number] => 06282123 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Method of fabricating, programming, and erasing a dual pocket two sided program/erase non-volatile memory cell' [patent_app_type] => 1 [patent_app_number] => 9/217646 [patent_app_country] => US [patent_app_date] => 1998-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 20 [patent_no_of_words] => 6912 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/282/06282123.pdf [firstpage_image] =>[orig_patent_app_number] => 217646 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/217646
Method of fabricating, programming, and erasing a dual pocket two sided program/erase non-volatile memory cell Dec 20, 1998 Issued
Array ( [id] => 4155169 [patent_doc_number] => 06031764 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-29 [patent_title] => 'Nonvolatile semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/208744 [patent_app_country] => US [patent_app_date] => 1998-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 7433 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/031/06031764.pdf [firstpage_image] =>[orig_patent_app_number] => 208744 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/208744
Nonvolatile semiconductor memory device Dec 9, 1998 Issued
Array ( [id] => 4110756 [patent_doc_number] => 06067258 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-23 [patent_title] => 'Operation mode determining circuit for semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/204544 [patent_app_country] => US [patent_app_date] => 1998-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 10 [patent_no_of_words] => 2692 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/067/06067258.pdf [firstpage_image] =>[orig_patent_app_number] => 204544 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/204544
Operation mode determining circuit for semiconductor memory device Dec 2, 1998 Issued
Array ( [id] => 4102805 [patent_doc_number] => 06134158 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-17 [patent_title] => 'Semiconductor device having a plurality of redundancy input/output lines' [patent_app_type] => 1 [patent_app_number] => 9/200452 [patent_app_country] => US [patent_app_date] => 1998-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3055 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/134/06134158.pdf [firstpage_image] =>[orig_patent_app_number] => 200452 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/200452
Semiconductor device having a plurality of redundancy input/output lines Nov 26, 1998 Issued
Array ( [id] => 4082297 [patent_doc_number] => 06069816 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-30 [patent_title] => 'High-speed responding data storing device for maintaining stored data without power supply' [patent_app_type] => 1 [patent_app_number] => 9/198841 [patent_app_country] => US [patent_app_date] => 1998-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 6563 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/069/06069816.pdf [firstpage_image] =>[orig_patent_app_number] => 198841 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/198841
High-speed responding data storing device for maintaining stored data without power supply Nov 23, 1998 Issued
Array ( [id] => 4117318 [patent_doc_number] => 06101151 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-08 [patent_title] => 'Synchronous semiconductor memory device employing temporary data output stop scheme' [patent_app_type] => 1 [patent_app_number] => 9/196245 [patent_app_country] => US [patent_app_date] => 1998-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 54 [patent_no_of_words] => 3409 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/101/06101151.pdf [firstpage_image] =>[orig_patent_app_number] => 196245 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/196245
Synchronous semiconductor memory device employing temporary data output stop scheme Nov 19, 1998 Issued
Array ( [id] => 3957185 [patent_doc_number] => 05982670 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Non-volatile memory device' [patent_app_type] => 1 [patent_app_number] => 9/196441 [patent_app_country] => US [patent_app_date] => 1998-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 5803 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/982/05982670.pdf [firstpage_image] =>[orig_patent_app_number] => 196441 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/196441
Non-volatile memory device Nov 19, 1998 Issued
Array ( [id] => 4424446 [patent_doc_number] => 06177828 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-23 [patent_title] => 'Charge pump circuit for a semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/195551 [patent_app_country] => US [patent_app_date] => 1998-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 23 [patent_no_of_words] => 5424 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/177/06177828.pdf [firstpage_image] =>[orig_patent_app_number] => 195551 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/195551
Charge pump circuit for a semiconductor memory device Nov 18, 1998 Issued
Array ( [id] => 4017681 [patent_doc_number] => 06005816 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-21 [patent_title] => 'Sense amplifier for complementary or non-complementary data signals' [patent_app_type] => 1 [patent_app_number] => 9/196568 [patent_app_country] => US [patent_app_date] => 1998-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5199 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/005/06005816.pdf [firstpage_image] =>[orig_patent_app_number] => 196568 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/196568
Sense amplifier for complementary or non-complementary data signals Nov 18, 1998 Issued
Array ( [id] => 4110347 [patent_doc_number] => 06097640 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'Memory and circuit for accessing data bits in a memory array in multi-data rate operation' [patent_app_type] => 1 [patent_app_number] => 9/195743 [patent_app_country] => US [patent_app_date] => 1998-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 4276 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/097/06097640.pdf [firstpage_image] =>[orig_patent_app_number] => 195743 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/195743
Memory and circuit for accessing data bits in a memory array in multi-data rate operation Nov 17, 1998 Issued
Array ( [id] => 4111017 [patent_doc_number] => 06067274 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-23 [patent_title] => 'Semiconductor memory device having a burst mode' [patent_app_type] => 1 [patent_app_number] => 9/190845 [patent_app_country] => US [patent_app_date] => 1998-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 5836 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/067/06067274.pdf [firstpage_image] =>[orig_patent_app_number] => 190845 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/190845
Semiconductor memory device having a burst mode Nov 11, 1998 Issued
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