
Son Luu Mai
Examiner (ID: 18155)
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2511, 2827, 2818 |
| Total Applications | 3063 |
| Issued Applications | 2917 |
| Pending Applications | 45 |
| Abandoned Applications | 107 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4120729
[patent_doc_number] => 06058063
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[patent_kind] => NA
[patent_issue_date] => 2000-05-02
[patent_title] => 'Integrated circuit memory devices having reduced power consumption requirements during standby mode operation'
[patent_app_type] => 1
[patent_app_number] => 9/187544
[patent_app_country] => US
[patent_app_date] => 1998-11-06
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Array
(
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[patent_issue_date] => 2001-01-30
[patent_title] => 'Reduced delay address decoders and decoding methods for integrated circuit memory devices'
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[patent_app_date] => 1998-11-03
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Array
(
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[patent_issue_date] => 2000-06-06
[patent_title] => 'Self-timed write reset pulse generation'
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Array
(
[id] => 4065229
[patent_doc_number] => 05970006
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-10-19
[patent_title] => 'Semiconductor memory device having cell array divided into a plurality of cell blocks'
[patent_app_type] => 1
[patent_app_number] => 9/182892
[patent_app_country] => US
[patent_app_date] => 1998-10-30
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Array
(
[id] => 4234368
[patent_doc_number] => 06011746
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[patent_issue_date] => 2000-01-04
[patent_title] => 'Word line driver for semiconductor memories'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/182943 | Word line driver for semiconductor memories | Oct 28, 1998 | Issued |
Array
(
[id] => 4110231
[patent_doc_number] => 06097633
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[patent_issue_date] => 2000-08-01
[patent_title] => 'Read circuit for non-volatile memories'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/182843 | Read circuit for non-volatile memories | Oct 28, 1998 | Issued |
Array
(
[id] => 4231579
[patent_doc_number] => 06088281
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[patent_title] => 'Semiconductor memory device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/175445 | Semiconductor memory device | Oct 19, 1998 | Issued |
Array
(
[id] => 4204915
[patent_doc_number] => 06044035
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[patent_issue_date] => 2000-03-28
[patent_title] => 'Semiconductor memory device having level-shifted precharge signal'
[patent_app_type] => 1
[patent_app_number] => 9/168673
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[patent_app_date] => 1998-10-09
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[firstpage_image] =>[orig_patent_app_number] => 168673
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/168673 | Semiconductor memory device having level-shifted precharge signal | Oct 8, 1998 | Issued |
Array
(
[id] => 3957238
[patent_doc_number] => 05982674
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-09
[patent_title] => 'Bi-directional data bus scheme with optimized read and write characters'
[patent_app_type] => 1
[patent_app_number] => 9/163341
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/163341 | Bi-directional data bus scheme with optimized read and write characters | Sep 29, 1998 | Issued |
Array
(
[id] => 4170389
[patent_doc_number] => 06104658
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[patent_issue_date] => 2000-08-15
[patent_title] => 'Distributed DRAM refreshing'
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Array
(
[id] => 3957658
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[patent_issue_date] => 1999-11-09
[patent_title] => 'Dynamic logic memory addressing circuits, systems, and methods with predecoders providing data and precharge control to decoders'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/159552 | Dynamic logic memory addressing circuits, systems, and methods with predecoders providing data and precharge control to decoders | Sep 23, 1998 | Issued |
Array
(
[id] => 3940312
[patent_doc_number] => 05953270
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Array
(
[id] => 4066684
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Array
(
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[patent_title] => 'Circuit for the generation of a high voltage for the programming or erasure of a memory'
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Array
(
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Array
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Array
(
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Array
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/140354 | Block write circuit and method for wide data path memory devices | Aug 25, 1998 | Issued |