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Son Luu Mai

Examiner (ID: 18155)

Most Active Art Unit
2827
Art Unit(s)
2511, 2827, 2818
Total Applications
3063
Issued Applications
2917
Pending Applications
45
Abandoned Applications
107

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4120729 [patent_doc_number] => 06058063 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-02 [patent_title] => 'Integrated circuit memory devices having reduced power consumption requirements during standby mode operation' [patent_app_type] => 1 [patent_app_number] => 9/187544 [patent_app_country] => US [patent_app_date] => 1998-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 1833 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/058/06058063.pdf [firstpage_image] =>[orig_patent_app_number] => 187544 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/187544
Integrated circuit memory devices having reduced power consumption requirements during standby mode operation Nov 5, 1998 Issued
Array ( [id] => 4309522 [patent_doc_number] => 06181635 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-30 [patent_title] => 'Reduced delay address decoders and decoding methods for integrated circuit memory devices' [patent_app_type] => 1 [patent_app_number] => 9/185154 [patent_app_country] => US [patent_app_date] => 1998-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 2964 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/181/06181635.pdf [firstpage_image] =>[orig_patent_app_number] => 185154 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/185154
Reduced delay address decoders and decoding methods for integrated circuit memory devices Nov 2, 1998 Issued
Array ( [id] => 4131314 [patent_doc_number] => 06072732 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-06 [patent_title] => 'Self-timed write reset pulse generation' [patent_app_type] => 1 [patent_app_number] => 9/183444 [patent_app_country] => US [patent_app_date] => 1998-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 5939 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/072/06072732.pdf [firstpage_image] =>[orig_patent_app_number] => 183444 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/183444
Self-timed write reset pulse generation Oct 29, 1998 Issued
Array ( [id] => 4065229 [patent_doc_number] => 05970006 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-19 [patent_title] => 'Semiconductor memory device having cell array divided into a plurality of cell blocks' [patent_app_type] => 1 [patent_app_number] => 9/182892 [patent_app_country] => US [patent_app_date] => 1998-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7435 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/970/05970006.pdf [firstpage_image] =>[orig_patent_app_number] => 182892 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/182892
Semiconductor memory device having cell array divided into a plurality of cell blocks Oct 29, 1998 Issued
Array ( [id] => 4234368 [patent_doc_number] => 06011746 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-04 [patent_title] => 'Word line driver for semiconductor memories' [patent_app_type] => 1 [patent_app_number] => 9/182943 [patent_app_country] => US [patent_app_date] => 1998-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 5333 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/011/06011746.pdf [firstpage_image] =>[orig_patent_app_number] => 182943 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/182943
Word line driver for semiconductor memories Oct 28, 1998 Issued
Array ( [id] => 4110231 [patent_doc_number] => 06097633 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'Read circuit for non-volatile memories' [patent_app_type] => 1 [patent_app_number] => 9/182843 [patent_app_country] => US [patent_app_date] => 1998-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2560 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/097/06097633.pdf [firstpage_image] =>[orig_patent_app_number] => 182843 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/182843
Read circuit for non-volatile memories Oct 28, 1998 Issued
Array ( [id] => 4231579 [patent_doc_number] => 06088281 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/175445 [patent_app_country] => US [patent_app_date] => 1998-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 8137 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/088/06088281.pdf [firstpage_image] =>[orig_patent_app_number] => 175445 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/175445
Semiconductor memory device Oct 19, 1998 Issued
Array ( [id] => 4204915 [patent_doc_number] => 06044035 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-28 [patent_title] => 'Semiconductor memory device having level-shifted precharge signal' [patent_app_type] => 1 [patent_app_number] => 9/168673 [patent_app_country] => US [patent_app_date] => 1998-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 23 [patent_no_of_words] => 12354 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/044/06044035.pdf [firstpage_image] =>[orig_patent_app_number] => 168673 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/168673
Semiconductor memory device having level-shifted precharge signal Oct 8, 1998 Issued
Array ( [id] => 3957238 [patent_doc_number] => 05982674 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Bi-directional data bus scheme with optimized read and write characters' [patent_app_type] => 1 [patent_app_number] => 9/163341 [patent_app_country] => US [patent_app_date] => 1998-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7508 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/982/05982674.pdf [firstpage_image] =>[orig_patent_app_number] => 163341 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/163341
Bi-directional data bus scheme with optimized read and write characters Sep 29, 1998 Issued
Array ( [id] => 4170389 [patent_doc_number] => 06104658 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-15 [patent_title] => 'Distributed DRAM refreshing' [patent_app_type] => 1 [patent_app_number] => 9/162943 [patent_app_country] => US [patent_app_date] => 1998-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 35 [patent_no_of_words] => 18380 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/104/06104658.pdf [firstpage_image] =>[orig_patent_app_number] => 162943 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/162943
Distributed DRAM refreshing Sep 28, 1998 Issued
Array ( [id] => 3957658 [patent_doc_number] => 05982702 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Dynamic logic memory addressing circuits, systems, and methods with predecoders providing data and precharge control to decoders' [patent_app_type] => 1 [patent_app_number] => 9/159552 [patent_app_country] => US [patent_app_date] => 1998-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 19955 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 410 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/982/05982702.pdf [firstpage_image] =>[orig_patent_app_number] => 159552 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/159552
Dynamic logic memory addressing circuits, systems, and methods with predecoders providing data and precharge control to decoders Sep 23, 1998 Issued
Array ( [id] => 3940312 [patent_doc_number] => 05953270 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-14 [patent_title] => 'Column redundancy circuit for a memory device' [patent_app_type] => 1 [patent_app_number] => 9/153343 [patent_app_country] => US [patent_app_date] => 1998-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3700 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 269 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/953/05953270.pdf [firstpage_image] =>[orig_patent_app_number] => 153343 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/153343
Column redundancy circuit for a memory device Sep 14, 1998 Issued
Array ( [id] => 4066684 [patent_doc_number] => RE036532 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-25 [patent_title] => 'Synchronous semiconductor memory device having an auto-precharge function' [patent_app_type] => 2 [patent_app_number] => 9/151414 [patent_app_country] => US [patent_app_date] => 1998-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4496 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 36 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/036/RE036532.pdf [firstpage_image] =>[orig_patent_app_number] => 151414 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/151414
Synchronous semiconductor memory device having an auto-precharge function Sep 9, 1998 Issued
Array ( [id] => 4012051 [patent_doc_number] => 05986936 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'Circuit for the generation of a high voltage for the programming or erasure of a memory' [patent_app_type] => 1 [patent_app_number] => 9/150954 [patent_app_country] => US [patent_app_date] => 1998-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 6599 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/986/05986936.pdf [firstpage_image] =>[orig_patent_app_number] => 150954 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/150954
Circuit for the generation of a high voltage for the programming or erasure of a memory Sep 9, 1998 Issued
Array ( [id] => 4144483 [patent_doc_number] => 06034903 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-07 [patent_title] => 'Semiconductor memory device with identification fuse' [patent_app_type] => 1 [patent_app_number] => 9/146753 [patent_app_country] => US [patent_app_date] => 1998-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 9379 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/034/06034903.pdf [firstpage_image] =>[orig_patent_app_number] => 146753 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/146753
Semiconductor memory device with identification fuse Sep 3, 1998 Issued
Array ( [id] => 4219179 [patent_doc_number] => 06028791 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-22 [patent_title] => 'Semiconductor memory device with improved data reading speed' [patent_app_type] => 1 [patent_app_number] => 9/143350 [patent_app_country] => US [patent_app_date] => 1998-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 10867 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/028/06028791.pdf [firstpage_image] =>[orig_patent_app_number] => 143350 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/143350
Semiconductor memory device with improved data reading speed Aug 27, 1998 Issued
Array ( [id] => 3960802 [patent_doc_number] => 05991232 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-23 [patent_title] => 'Clock synchronous memory embedded semiconductor integrated circuit device' [patent_app_type] => 1 [patent_app_number] => 9/143253 [patent_app_country] => US [patent_app_date] => 1998-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 32 [patent_no_of_words] => 14302 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/991/05991232.pdf [firstpage_image] =>[orig_patent_app_number] => 143253 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/143253
Clock synchronous memory embedded semiconductor integrated circuit device Aug 27, 1998 Issued
Array ( [id] => 4054551 [patent_doc_number] => 05912849 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-15 [patent_title] => 'Write Protection for a non-volatile memory' [patent_app_type] => 1 [patent_app_number] => 9/141564 [patent_app_country] => US [patent_app_date] => 1998-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 24 [patent_no_of_words] => 10933 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/912/05912849.pdf [firstpage_image] =>[orig_patent_app_number] => 141564 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/141564
Write Protection for a non-volatile memory Aug 27, 1998 Issued
Array ( [id] => 4110079 [patent_doc_number] => 06097623 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'Ferroelectric memory device having two columns of memory cells precharged to separate voltages' [patent_app_type] => 1 [patent_app_number] => 9/125545 [patent_app_country] => US [patent_app_date] => 1998-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 38 [patent_no_of_words] => 13709 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/097/06097623.pdf [firstpage_image] =>[orig_patent_app_number] => 125545 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/125545
Ferroelectric memory device having two columns of memory cells precharged to separate voltages Aug 27, 1998 Issued
Array ( [id] => 4234070 [patent_doc_number] => 06011727 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-04 [patent_title] => 'Block write circuit and method for wide data path memory devices' [patent_app_type] => 1 [patent_app_number] => 9/140354 [patent_app_country] => US [patent_app_date] => 1998-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7960 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/011/06011727.pdf [firstpage_image] =>[orig_patent_app_number] => 140354 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/140354
Block write circuit and method for wide data path memory devices Aug 25, 1998 Issued
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